| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/net/dsa/realtek.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Realtek switches for unmanaged switches |
| 8 | |
| 9 | allOf: |
| 10 | - $ref: dsa.yaml#/$defs/ethernet-ports |
| 11 | |
| 12 | maintainers: |
| 13 | - Linus Walleij <linus.walleij@linaro.org> |
| 14 | |
| 15 | description: |
| 16 | Realtek advertises these chips as fast/gigabit switches or unmanaged |
| 17 | switches. They can be controlled using different interfaces, like SMI, |
| 18 | MDIO or SPI. |
| 19 | |
| 20 | The SMI "Simple Management Interface" is a two-wire protocol using |
| 21 | bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does |
| 22 | not use the MDIO protocol. This binding defines how to specify the |
| 23 | SMI-based Realtek devices. The realtek-smi driver is a platform driver |
| 24 | and it must be inserted inside a platform node. |
| 25 | |
| 26 | The MDIO-connected switches use MDIO protocol to access their registers. |
| 27 | The realtek-mdio driver is an MDIO driver and it must be inserted inside |
| 28 | an MDIO node. |
| 29 | |
| 30 | The compatible string is only used to identify which (silicon) family the |
| 31 | switch belongs to. Roughly speaking, a family is any set of Realtek switches |
| 32 | whose chip identification register(s) have a common location and semantics. |
| 33 | The different models in a given family can be automatically disambiguated by |
| 34 | parsing the chip identification register(s) according to the given family, |
| 35 | avoiding the need for a unique compatible string for each model. |
| 36 | |
| 37 | properties: |
| 38 | compatible: |
| 39 | enum: |
| 40 | - realtek,rtl8365mb |
| 41 | - realtek,rtl8366rb |
| 42 | description: | |
| 43 | realtek,rtl8365mb: |
| 44 | Use with models RTL8363NB, RTL8363NB-VB, RTL8363SC, RTL8363SC-VB, |
| 45 | RTL8364NB, RTL8364NB-VB, RTL8365MB, RTL8366SC, RTL8367RB-VB, RTL8367S, |
| 46 | RTL8367SB, RTL8370MB, RTL8310SR |
| 47 | realtek,rtl8366rb: |
| 48 | Use with models RTL8366RB, RTL8366S |
| 49 | |
| 50 | mdc-gpios: |
| 51 | description: GPIO line for the MDC clock line. |
| 52 | maxItems: 1 |
| 53 | |
| 54 | mdio-gpios: |
| 55 | description: GPIO line for the MDIO data line. |
| 56 | maxItems: 1 |
| 57 | |
| 58 | reset-gpios: |
| 59 | description: GPIO to be used to reset the whole device |
| 60 | maxItems: 1 |
| 61 | |
| 62 | realtek,disable-leds: |
| 63 | type: boolean |
| 64 | description: | |
| 65 | if the LED drivers are not used in the hardware design, |
| 66 | this will disable them so they are not turned on |
| 67 | and wasting power. |
| 68 | |
| 69 | interrupt-controller: |
| 70 | type: object |
| 71 | additionalProperties: false |
| 72 | |
| 73 | description: | |
| 74 | This defines an interrupt controller with an IRQ line (typically |
| 75 | a GPIO) that will demultiplex and handle the interrupt from the single |
| 76 | interrupt line coming out of one of the Realtek switch chips. It most |
| 77 | importantly provides link up/down interrupts to the PHY blocks inside |
| 78 | the ASIC. |
| 79 | |
| 80 | properties: |
| 81 | |
| 82 | interrupt-controller: true |
| 83 | |
| 84 | interrupts: |
| 85 | maxItems: 1 |
| 86 | description: |
| 87 | A single IRQ line from the switch, either active LOW or HIGH |
| 88 | |
| 89 | '#address-cells': |
| 90 | const: 0 |
| 91 | |
| 92 | '#interrupt-cells': |
| 93 | const: 1 |
| 94 | |
| 95 | required: |
| 96 | - interrupt-controller |
| 97 | - '#address-cells' |
| 98 | - '#interrupt-cells' |
| 99 | |
| 100 | mdio: |
| 101 | $ref: /schemas/net/mdio.yaml# |
| 102 | unevaluatedProperties: false |
| 103 | |
| 104 | properties: |
| 105 | compatible: |
| 106 | const: realtek,smi-mdio |
| 107 | |
| 108 | if: |
| 109 | required: |
| 110 | - reg |
| 111 | |
| 112 | then: |
| 113 | $ref: /schemas/spi/spi-peripheral-props.yaml# |
| 114 | not: |
| 115 | required: |
| 116 | - mdc-gpios |
| 117 | - mdio-gpios |
| 118 | - mdio |
| 119 | |
| 120 | properties: |
| 121 | mdc-gpios: false |
| 122 | mdio-gpios: false |
| 123 | mdio: false |
| 124 | |
| 125 | else: |
| 126 | required: |
| 127 | - mdc-gpios |
| 128 | - mdio-gpios |
| 129 | - mdio |
| 130 | - reset-gpios |
| 131 | |
| 132 | required: |
| 133 | - compatible |
| 134 | |
| 135 | # - mdc-gpios |
| 136 | # - mdio-gpios |
| 137 | # - reset-gpios |
| 138 | # - mdio |
| 139 | |
| 140 | unevaluatedProperties: false |
| 141 | |
| 142 | examples: |
| 143 | - | |
| 144 | #include <dt-bindings/gpio/gpio.h> |
| 145 | #include <dt-bindings/interrupt-controller/irq.h> |
| 146 | |
| 147 | platform { |
| 148 | switch { |
| 149 | compatible = "realtek,rtl8366rb"; |
| 150 | /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */ |
| 151 | mdc-gpios = <&gpio0 21 GPIO_ACTIVE_HIGH>; |
| 152 | mdio-gpios = <&gpio0 22 GPIO_ACTIVE_HIGH>; |
| 153 | reset-gpios = <&gpio0 14 GPIO_ACTIVE_LOW>; |
| 154 | |
| 155 | switch_intc1: interrupt-controller { |
| 156 | /* GPIO 15 provides the interrupt */ |
| 157 | interrupt-parent = <&gpio0>; |
| 158 | interrupts = <15 IRQ_TYPE_LEVEL_LOW>; |
| 159 | interrupt-controller; |
| 160 | #address-cells = <0>; |
| 161 | #interrupt-cells = <1>; |
| 162 | }; |
| 163 | |
| 164 | ports { |
| 165 | #address-cells = <1>; |
| 166 | #size-cells = <0>; |
| 167 | port@0 { |
| 168 | reg = <0>; |
| 169 | label = "lan0"; |
| 170 | phy-handle = <&phy0>; |
| 171 | }; |
| 172 | port@1 { |
| 173 | reg = <1>; |
| 174 | label = "lan1"; |
| 175 | phy-handle = <&phy1>; |
| 176 | }; |
| 177 | port@2 { |
| 178 | reg = <2>; |
| 179 | label = "lan2"; |
| 180 | phy-handle = <&phy2>; |
| 181 | }; |
| 182 | port@3 { |
| 183 | reg = <3>; |
| 184 | label = "lan3"; |
| 185 | phy-handle = <&phy3>; |
| 186 | }; |
| 187 | port@4 { |
| 188 | reg = <4>; |
| 189 | label = "wan"; |
| 190 | phy-handle = <&phy4>; |
| 191 | }; |
| 192 | port@5 { |
| 193 | reg = <5>; |
| 194 | ethernet = <&gmac0>; |
| 195 | phy-mode = "rgmii"; |
| 196 | fixed-link { |
| 197 | speed = <1000>; |
| 198 | full-duplex; |
| 199 | }; |
| 200 | }; |
| 201 | }; |
| 202 | |
| 203 | mdio { |
| 204 | compatible = "realtek,smi-mdio"; |
| 205 | #address-cells = <1>; |
| 206 | #size-cells = <0>; |
| 207 | |
| 208 | phy0: ethernet-phy@0 { |
| 209 | reg = <0>; |
| 210 | interrupt-parent = <&switch_intc1>; |
| 211 | interrupts = <0>; |
| 212 | }; |
| 213 | phy1: ethernet-phy@1 { |
| 214 | reg = <1>; |
| 215 | interrupt-parent = <&switch_intc1>; |
| 216 | interrupts = <1>; |
| 217 | }; |
| 218 | phy2: ethernet-phy@2 { |
| 219 | reg = <2>; |
| 220 | interrupt-parent = <&switch_intc1>; |
| 221 | interrupts = <2>; |
| 222 | }; |
| 223 | phy3: ethernet-phy@3 { |
| 224 | reg = <3>; |
| 225 | interrupt-parent = <&switch_intc1>; |
| 226 | interrupts = <3>; |
| 227 | }; |
| 228 | phy4: ethernet-phy@4 { |
| 229 | reg = <4>; |
| 230 | interrupt-parent = <&switch_intc1>; |
| 231 | interrupts = <12>; |
| 232 | }; |
| 233 | }; |
| 234 | }; |
| 235 | }; |
| 236 | |
| 237 | - | |
| 238 | #include <dt-bindings/gpio/gpio.h> |
| 239 | #include <dt-bindings/interrupt-controller/irq.h> |
| 240 | |
| 241 | platform { |
| 242 | switch { |
| 243 | compatible = "realtek,rtl8365mb"; |
| 244 | mdc-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; |
| 245 | mdio-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; |
| 246 | reset-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; |
| 247 | |
| 248 | switch_intc2: interrupt-controller { |
| 249 | interrupt-parent = <&gpio5>; |
| 250 | interrupts = <1 IRQ_TYPE_LEVEL_LOW>; |
| 251 | interrupt-controller; |
| 252 | #address-cells = <0>; |
| 253 | #interrupt-cells = <1>; |
| 254 | }; |
| 255 | |
| 256 | ports { |
| 257 | #address-cells = <1>; |
| 258 | #size-cells = <0>; |
| 259 | port@0 { |
| 260 | reg = <0>; |
| 261 | label = "swp0"; |
| 262 | phy-handle = <ðphy0>; |
| 263 | }; |
| 264 | port@1 { |
| 265 | reg = <1>; |
| 266 | label = "swp1"; |
| 267 | phy-handle = <ðphy1>; |
| 268 | }; |
| 269 | port@2 { |
| 270 | reg = <2>; |
| 271 | label = "swp2"; |
| 272 | phy-handle = <ðphy2>; |
| 273 | }; |
| 274 | port@3 { |
| 275 | reg = <3>; |
| 276 | label = "swp3"; |
| 277 | phy-handle = <ðphy3>; |
| 278 | }; |
| 279 | port@6 { |
| 280 | reg = <6>; |
| 281 | ethernet = <&fec1>; |
| 282 | phy-mode = "rgmii"; |
| 283 | tx-internal-delay-ps = <2000>; |
| 284 | rx-internal-delay-ps = <2000>; |
| 285 | |
| 286 | fixed-link { |
| 287 | speed = <1000>; |
| 288 | full-duplex; |
| 289 | pause; |
| 290 | }; |
| 291 | }; |
| 292 | }; |
| 293 | |
| 294 | mdio { |
| 295 | compatible = "realtek,smi-mdio"; |
| 296 | #address-cells = <1>; |
| 297 | #size-cells = <0>; |
| 298 | |
| 299 | ethphy0: ethernet-phy@0 { |
| 300 | reg = <0>; |
| 301 | interrupt-parent = <&switch_intc2>; |
| 302 | interrupts = <0>; |
| 303 | }; |
| 304 | ethphy1: ethernet-phy@1 { |
| 305 | reg = <1>; |
| 306 | interrupt-parent = <&switch_intc2>; |
| 307 | interrupts = <1>; |
| 308 | }; |
| 309 | ethphy2: ethernet-phy@2 { |
| 310 | reg = <2>; |
| 311 | interrupt-parent = <&switch_intc2>; |
| 312 | interrupts = <2>; |
| 313 | }; |
| 314 | ethphy3: ethernet-phy@3 { |
| 315 | reg = <3>; |
| 316 | interrupt-parent = <&switch_intc2>; |
| 317 | interrupts = <3>; |
| 318 | }; |
| 319 | }; |
| 320 | }; |
| 321 | }; |
| 322 | |
| 323 | - | |
| 324 | #include <dt-bindings/gpio/gpio.h> |
| 325 | #include <dt-bindings/interrupt-controller/irq.h> |
| 326 | |
| 327 | mdio { |
| 328 | #address-cells = <1>; |
| 329 | #size-cells = <0>; |
| 330 | |
| 331 | switch@29 { |
| 332 | compatible = "realtek,rtl8365mb"; |
| 333 | reg = <29>; |
| 334 | |
| 335 | reset-gpios = <&gpio2 20 GPIO_ACTIVE_LOW>; |
| 336 | |
| 337 | switch_intc3: interrupt-controller { |
| 338 | interrupt-parent = <&gpio0>; |
| 339 | interrupts = <11 IRQ_TYPE_EDGE_FALLING>; |
| 340 | interrupt-controller; |
| 341 | #address-cells = <0>; |
| 342 | #interrupt-cells = <1>; |
| 343 | }; |
| 344 | |
| 345 | ports { |
| 346 | #address-cells = <1>; |
| 347 | #size-cells = <0>; |
| 348 | |
| 349 | port@0 { |
| 350 | reg = <0>; |
| 351 | label = "lan4"; |
| 352 | }; |
| 353 | |
| 354 | port@1 { |
| 355 | reg = <1>; |
| 356 | label = "lan3"; |
| 357 | }; |
| 358 | |
| 359 | port@2 { |
| 360 | reg = <2>; |
| 361 | label = "lan2"; |
| 362 | }; |
| 363 | |
| 364 | port@3 { |
| 365 | reg = <3>; |
| 366 | label = "lan1"; |
| 367 | }; |
| 368 | |
| 369 | port@4 { |
| 370 | reg = <4>; |
| 371 | label = "wan"; |
| 372 | }; |
| 373 | |
| 374 | port@7 { |
| 375 | reg = <7>; |
| 376 | ethernet = <ðernet>; |
| 377 | phy-mode = "rgmii"; |
| 378 | tx-internal-delay-ps = <2000>; |
| 379 | rx-internal-delay-ps = <0>; |
| 380 | |
| 381 | fixed-link { |
| 382 | speed = <1000>; |
| 383 | full-duplex; |
| 384 | }; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
| 388 | }; |