| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/display/msm/qcom,mdp5.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: Qualcomm Adreno/Snapdragon Mobile Display controller (MDP5) |
| 8 | |
| 9 | description: |
| 10 | MDP5 display controller found in SoCs like MSM8974, APQ8084, MSM8916, MSM8994 |
| 11 | and MSM8996. |
| 12 | |
| 13 | maintainers: |
| 14 | - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> |
| 15 | - Rob Clark <robdclark@gmail.com> |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | oneOf: |
| 20 | - const: qcom,mdp5 |
| 21 | deprecated: true |
| 22 | - items: |
| 23 | - enum: |
| 24 | - qcom,apq8084-mdp5 |
| 25 | - qcom,msm8226-mdp5 |
| 26 | - qcom,msm8916-mdp5 |
| 27 | - qcom,msm8917-mdp5 |
| 28 | - qcom,msm8953-mdp5 |
| 29 | - qcom,msm8974-mdp5 |
| 30 | - qcom,msm8976-mdp5 |
| 31 | - qcom,msm8994-mdp5 |
| 32 | - qcom,msm8996-mdp5 |
| 33 | - qcom,sdm630-mdp5 |
| 34 | - qcom,sdm660-mdp5 |
| 35 | - const: qcom,mdp5 |
| 36 | |
| 37 | $nodename: |
| 38 | pattern: '^display-controller@[0-9a-f]+$' |
| 39 | |
| 40 | reg: |
| 41 | maxItems: 1 |
| 42 | |
| 43 | reg-names: |
| 44 | items: |
| 45 | - const: mdp_phys |
| 46 | |
| 47 | interrupts: |
| 48 | maxItems: 1 |
| 49 | |
| 50 | clocks: |
| 51 | minItems: 4 |
| 52 | maxItems: 7 |
| 53 | |
| 54 | clock-names: |
| 55 | oneOf: |
| 56 | - minItems: 4 |
| 57 | items: |
| 58 | - const: iface |
| 59 | - const: bus |
| 60 | - const: core |
| 61 | - const: vsync |
| 62 | - const: lut |
| 63 | - const: tbu |
| 64 | - const: tbu_rt |
| 65 | # MSM8996 has additional iommu clock |
| 66 | - items: |
| 67 | - const: iface |
| 68 | - const: bus |
| 69 | - const: core |
| 70 | - const: iommu |
| 71 | - const: vsync |
| 72 | |
| 73 | interconnects: |
| 74 | minItems: 1 |
| 75 | items: |
| 76 | - description: Interconnect path from mdp0 (or a single mdp) port to the data bus |
| 77 | - description: Interconnect path from mdp1 port to the data bus |
| 78 | - description: Interconnect path from rotator port to the data bus |
| 79 | |
| 80 | interconnect-names: |
| 81 | minItems: 1 |
| 82 | items: |
| 83 | - const: mdp0-mem |
| 84 | - const: mdp1-mem |
| 85 | - const: rotator-mem |
| 86 | |
| 87 | iommus: |
| 88 | items: |
| 89 | - description: apps SMMU with the Stream-ID mask for Hard-Fail port0 |
| 90 | |
| 91 | power-domains: |
| 92 | maxItems: 1 |
| 93 | |
| 94 | operating-points-v2: true |
| 95 | opp-table: |
| 96 | type: object |
| 97 | |
| 98 | ports: |
| 99 | $ref: /schemas/graph.yaml#/properties/ports |
| 100 | description: > |
| 101 | Contains the list of output ports from DPU device. These ports |
| 102 | connect to interfaces that are external to the DPU hardware, |
| 103 | such as DSI, DP etc. MDP5 devices support up to 4 ports: |
| 104 | one or two DSI ports, HDMI and eDP. |
| 105 | |
| 106 | patternProperties: |
| 107 | "^port@[0-3]+$": |
| 108 | $ref: /schemas/graph.yaml#/properties/port |
| 109 | |
| 110 | # at least one port is required |
| 111 | required: |
| 112 | - port@0 |
| 113 | |
| 114 | required: |
| 115 | - compatible |
| 116 | - reg |
| 117 | - reg-names |
| 118 | - clocks |
| 119 | - clock-names |
| 120 | - ports |
| 121 | |
| 122 | additionalProperties: false |
| 123 | |
| 124 | examples: |
| 125 | - | |
| 126 | #include <dt-bindings/clock/qcom,gcc-msm8916.h> |
| 127 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 128 | display-controller@1a01000 { |
| 129 | compatible = "qcom,mdp5"; |
| 130 | reg = <0x1a01000 0x90000>; |
| 131 | reg-names = "mdp_phys"; |
| 132 | |
| 133 | interrupt-parent = <&mdss>; |
| 134 | interrupts = <0>; |
| 135 | |
| 136 | clocks = <&gcc GCC_MDSS_AHB_CLK>, |
| 137 | <&gcc GCC_MDSS_AXI_CLK>, |
| 138 | <&gcc GCC_MDSS_MDP_CLK>, |
| 139 | <&gcc GCC_MDSS_VSYNC_CLK>; |
| 140 | clock-names = "iface", |
| 141 | "bus", |
| 142 | "core", |
| 143 | "vsync"; |
| 144 | |
| 145 | ports { |
| 146 | #address-cells = <1>; |
| 147 | #size-cells = <0>; |
| 148 | |
| 149 | port@0 { |
| 150 | reg = <0>; |
| 151 | endpoint { |
| 152 | remote-endpoint = <&dsi0_in>; |
| 153 | }; |
| 154 | }; |
| 155 | }; |
| 156 | }; |
| 157 | ... |