| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) |
| 2 | # Copyright 2020 thingy.jp. |
| 3 | %YAML 1.2 |
| 4 | --- |
| 5 | $id: http://devicetree.org/schemas/arm/mstar/mstar,l3bridge.yaml# |
| 6 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 7 | |
| 8 | title: MStar/SigmaStar Armv7 SoC l3bridge |
| 9 | |
| 10 | maintainers: |
| 11 | - Daniel Palmer <daniel@thingy.jp> |
| 12 | |
| 13 | description: | |
| 14 | MStar/SigmaStar's Armv7 SoCs have a pipeline in the interface |
| 15 | between the CPU and memory. This means that before DMA capable |
| 16 | devices are allowed to run the pipeline must be flushed to ensure |
| 17 | everything is in memory. |
| 18 | |
| 19 | The l3bridge region contains registers that allow such a flush |
| 20 | to be triggered. |
| 21 | |
| 22 | This node is used by the platform code to find where the registers |
| 23 | are and install a barrier that triggers the required pipeline flush. |
| 24 | |
| 25 | properties: |
| 26 | compatible: |
| 27 | items: |
| 28 | - const: mstar,l3bridge |
| 29 | |
| 30 | reg: |
| 31 | maxItems: 1 |
| 32 | |
| 33 | required: |
| 34 | - compatible |
| 35 | - reg |
| 36 | |
| 37 | additionalProperties: false |
| 38 | |
| 39 | examples: |
| 40 | - | |
| 41 | l3bridge: l3bridge@1f204400 { |
| 42 | compatible = "mstar,l3bridge"; |
| 43 | reg = <0x1f204400 0x200>; |
| 44 | }; |