blob: cd9591a9e3243156bf3c021f030660bb3aab25bf [file] [log] [blame]
Fabio Estevamebc8fcc2019-12-09 10:43:03 -03001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Freescale Semiconductor, Inc.
4 */
5
Tom Riniabb9a042024-05-18 20:20:43 -06006#include <common.h>
Simon Glass97589732020-05-10 11:40:02 -06007#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06008#include <asm/global_data.h>
Fabio Estevamebc8fcc2019-12-09 10:43:03 -03009#include <asm/io.h>
10#include <asm/arch/sys_proto.h>
11#include <asm/arch/mx7ulp-pins.h>
12#include <asm/arch/iomux.h>
13#include <asm/gpio.h>
14
15DECLARE_GLOBAL_DATA_PTR;
16
17#define UART_PAD_CTRL (PAD_CTL_PUS_UP)
18
19int dram_init(void)
20{
21 gd->ram_size = imx_ddr_size();
22
Ricardo Salveti5f371cc2021-08-25 18:47:18 +030023#ifdef CONFIG_OPTEE_TZDRAM_SIZE
24 gd->ram_size -= CONFIG_OPTEE_TZDRAM_SIZE;
25#endif
26
Fabio Estevamebc8fcc2019-12-09 10:43:03 -030027 return 0;
28}
29
30static iomux_cfg_t const lpuart4_pads[] = {
31 MX7ULP_PAD_PTC3__LPUART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
32 MX7ULP_PAD_PTC2__LPUART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
33};
34
35static void setup_iomux_uart(void)
36{
37 mx7ulp_iomux_setup_multiple_pads(lpuart4_pads,
38 ARRAY_SIZE(lpuart4_pads));
39}
40
41int board_early_init_f(void)
42{
43 setup_iomux_uart();
44
45 return 0;
46}
47
48int board_init(void)
49{
50 /* address of boot parameters */
51 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
52
53 return 0;
54}
Ricardo Salveti02192502021-09-12 17:32:57 +030055
56#ifdef CONFIG_SPL_BUILD
57#include <spl.h>
58
59#ifdef CONFIG_SPL_LOAD_FIT
60int board_fit_config_name_match(const char *name)
61{
62 if (!strcmp(name, "imx7ulp-com"))
63 return 0;
64
65 return -1;
66}
67#endif
68
69void spl_board_init(void)
70{
71 preloader_console_init();
72}
73
74void board_init_f(ulong dummy)
75{
76 arch_cpu_init();
77
78 board_early_init_f();
79}
80#endif