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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Graeme Russa875dda2011-12-23 16:51:29 +11002/*
3 * (C) Copyright 2011
4 * Graeme Russ, <graeme.russ@gmail.com>
Graeme Russa875dda2011-12-23 16:51:29 +11005 */
Bin Meng535109a2015-08-13 00:29:10 -07006
Tom Riniabb9a042024-05-18 20:20:43 -06007#include <common.h>
Simon Glass6980b6b2019-11-14 12:57:45 -07008#include <init.h>
Simon Glass3ba929a2020-10-30 21:38:53 -06009#include <asm/global_data.h>
Masahiro Yamada56a931c2016-09-21 11:28:55 +090010#include <linux/errno.h>
Simon Glass004ba172015-01-01 16:18:11 -070011#include <asm/mtrr.h>
Graeme Russa875dda2011-12-23 16:51:29 +110012
13DECLARE_GLOBAL_DATA_PTR;
14
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110015int init_cache_f_r(void)
16{
Simon Glassa72a7ab2019-09-25 08:56:49 -060017 bool do_mtrr = CONFIG_IS_ENABLED(X86_32BIT_INIT) ||
Simon Glass37da5752023-09-07 09:58:19 -060018 IS_ENABLED(CONFIG_FSP_VERSION2) ||
19 (IS_ENABLED(CONFIG_TPL) && IS_ENABLED(CONFIG_HAVE_MRC));
Simon Glass004ba172015-01-01 16:18:11 -070020 int ret;
21
Simon Glass76f8bbe2021-06-27 17:51:03 -060022 /*
23 * Supported configurations:
24 *
Bin Meng4a3f3912023-07-31 07:56:02 -060025 * booting from slimbootloader - MTRRs are already set up
Simon Glass76f8bbe2021-06-27 17:51:03 -060026 * booting with FSPv1 - MTRRs are already set up
Simon Glass37da5752023-09-07 09:58:19 -060027 * booting with FSPv2 or MRC - MTRRs must be set here
Simon Glass76f8bbe2021-06-27 17:51:03 -060028 * booting from coreboot - in this case there is no SPL, so we set up
29 * the MTRRs here
Simon Glass76f8bbe2021-06-27 17:51:03 -060030 */
Bin Meng4a3f3912023-07-31 07:56:02 -060031 do_mtrr &= !IS_ENABLED(CONFIG_FSP_VERSION1) &&
Simon Glassa72a7ab2019-09-25 08:56:49 -060032 !IS_ENABLED(CONFIG_SYS_SLIMBOOTLOADER);
33
34 if (do_mtrr) {
35 ret = mtrr_commit(false);
36 /*
37 * If MTRR MSR is not implemented by the processor, just ignore
38 * it
39 */
40 if (ret && ret != -ENOSYS)
41 return ret;
42 }
43
Graeme Russ3fb4f9e2011-12-23 21:14:22 +110044 /* Initialise the CPU cache(s) */
45 return init_cache();
46}