| Prabhakar Kushwaha | 63956d5 | 2012-04-24 20:17:15 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2011-2012 Freescale Semiconductor, Inc. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #include <common.h> |
| 24 | #include <asm/mmu.h> |
| 25 | |
| 26 | struct fsl_e_tlb_entry tlb_table[] = { |
| 27 | /* TLB 0 - for temp stack in cache */ |
| 28 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
| 29 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 30 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 31 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , |
| 32 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
| 33 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 34 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 35 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , |
| 36 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
| 37 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 38 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 39 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , |
| 40 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
| 41 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 42 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 43 | |
| 44 | /* TLB 1 */ |
| 45 | /* *I*** - Covers boot page */ |
| 46 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
| 47 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 48 | 0, 0, BOOKE_PAGESZ_4K, 1), |
| 49 | |
| 50 | /* *I*G* - CCSRBAR (PA) */ |
| 51 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
| 52 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 53 | 0, 1, BOOKE_PAGESZ_1M, 1), |
| 54 | |
| 55 | #if defined(CONFIG_SYS_RAMBOOT) |
| 56 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
| 57 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 58 | 0, 8, BOOKE_PAGESZ_1G, 1), |
| 59 | #endif |
| 60 | |
| 61 | SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, |
| 62 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 63 | 0, 3, BOOKE_PAGESZ_1M, 1) |
| 64 | |
| 65 | }; |
| 66 | |
| 67 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |