Jean-Christophe PLAGNIOL-VILLARD | c026877 | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 1 | # |
| 2 | # (C) Copyright 2008 |
| 3 | # Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | # |
Wolfgang Denk | d79de1d | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | # SPDX-License-Identifier: GPL-2.0+ |
Jean-Christophe PLAGNIOL-VILLARD | c026877 | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 6 | # |
| 7 | |
Masahiro Yamada | 5594ce4 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 8 | obj-y += fpga.o |
| 9 | obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o |
| 10 | obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o |
| 11 | obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o |
| 12 | obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o |
Siva Durga Prasad Paladugu | 460fdce | 2016-01-13 16:25:37 +0530 | [diff] [blame] | 13 | obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o |
Masahiro Yamada | 5594ce4 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 14 | obj-$(CONFIG_FPGA_XILINX) += xilinx.o |
| 15 | obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o |
Jean-Christophe PLAGNIOL-VILLARD | c026877 | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 16 | ifdef CONFIG_FPGA_ALTERA |
Masahiro Yamada | 5594ce4 | 2013-10-17 17:34:57 +0900 | [diff] [blame] | 17 | obj-y += altera.o |
| 18 | obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o |
| 19 | obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o |
| 20 | obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o |
Stefan Roese | d919d72 | 2016-02-12 13:48:02 +0100 | [diff] [blame] | 21 | obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o |
Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 22 | obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o |
Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 23 | obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o |
Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 24 | obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o |
Jean-Christophe PLAGNIOL-VILLARD | c026877 | 2008-10-31 12:26:55 +0100 | [diff] [blame] | 25 | endif |