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wdenk0157ced2002-10-21 17:04:47 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#ifndef __ASM_GBL_DATA_H
25#define __ASM_GBL_DATA_H
Eran Liberty9095d4a2005-07-28 10:08:46 -050026
27#include "asm/types.h"
28
wdenk0157ced2002-10-21 17:04:47 +000029/*
30 * The following data structure is placed in some memory wich is
31 * available very early after boot (like DPRAM on MPC8xx/MPC82xx, or
32 * some locked parts of the data cache) to allow for a minimum set of
33 * global variables during system initialization (until we have set
34 * up the memory controller so that we can use RAM).
35 *
36 * Keep it *SMALL* and remember to set CFG_GBL_DATA_SIZE > sizeof(gd_t)
37 */
38
39typedef struct global_data {
40 bd_t *bd;
41 unsigned long flags;
42 unsigned long baudrate;
Bryan O'Donoghue86c8d742008-02-17 22:57:47 +000043 unsigned long cpu_clk; /* CPU clock in Hz! */
wdenk0157ced2002-10-21 17:04:47 +000044 unsigned long bus_clk;
Bryan O'Donoghue86c8d742008-02-17 22:57:47 +000045#if defined(CONFIG_8xx)
46 unsigned long brg_clk;
47#endif
Jon Loeligerf5ad3782005-07-23 10:37:35 -050048#if defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +000049 /* There are many clocks on the MPC8260 - see page 9-5 */
50 unsigned long vco_out;
51 unsigned long cpm_clk;
52 unsigned long scc_clk;
53 unsigned long brg_clk;
54#endif
roy zangd136d662006-11-02 18:49:51 +080055 unsigned long mem_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050056#if defined(CONFIG_MPC83XX)
57 /* There are other clocks in the MPC83XX */
58 u32 csb_clk;
Dave Liu5245ff52007-09-18 12:36:11 +080059#if defined(CONFIG_MPC834X) || defined(CONFIG_MPC831X) || defined(CONFIG_MPC837X)
Eran Liberty9095d4a2005-07-28 10:08:46 -050060 u32 tsec1_clk;
61 u32 tsec2_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050062 u32 usbdr_clk;
Scott Woodbeb638a2007-04-16 14:34:18 -050063#endif
64#if defined (CONFIG_MPC834X)
65 u32 usbmph_clk;
Kumar Galab7870e72007-01-30 14:08:30 -060066#endif /* CONFIG_MPC834X */
Dave Liu0ce4fef2008-01-10 23:04:13 +080067#if defined(CONFIG_MPC8315)
Dave Liue0cfec82007-09-18 12:36:58 +080068 u32 tdm_clk;
69#endif
Dave Liu5245ff52007-09-18 12:36:11 +080070#if defined(CONFIG_MPC837X)
71 u32 sdhc_clk;
72#endif
Dave Liua46daea2006-11-03 19:33:44 -060073 u32 core_clk;
Eran Liberty9095d4a2005-07-28 10:08:46 -050074 u32 enc_clk;
75 u32 lbiu_clk;
76 u32 lclk_clk;
77 u32 ddr_clk;
Rafal Jaworowski384da5e2005-10-17 02:39:53 +020078 u32 pci_clk;
Dave Liu5245ff52007-09-18 12:36:11 +080079#if defined(CONFIG_MPC837X)
80 u32 pciexp1_clk;
81 u32 pciexp2_clk;
Dave Liue0cfec82007-09-18 12:36:58 +080082#endif
83#if defined(CONFIG_MPC837X) || defined(CONFIG_MPC8315)
Dave Liu5245ff52007-09-18 12:36:11 +080084 u32 sata_clk;
85#endif
Andy Flemingee0e9172007-08-14 00:14:25 -050086#if defined(CONFIG_MPC8360)
87 u32 ddr_sec_clk;
88#endif /* CONFIG_MPC8360 */
89#endif
Timur Tabic1499f482008-01-09 14:35:26 -060090#if defined(CONFIG_MPC83XX) || defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
91 u32 i2c1_clk;
92 u32 i2c2_clk;
93#endif
Dave Liua46daea2006-11-03 19:33:44 -060094#if defined(CONFIG_QE)
95 u32 qe_clk;
96 u32 brg_clk;
Dave Liue732e9c2006-11-03 12:11:15 -060097 uint mp_alloc_base;
98 uint mp_alloc_top;
Dave Liua46daea2006-11-03 19:33:44 -060099#endif /* CONFIG_QE */
wdenkbe9c1cb2004-02-24 02:00:03 +0000100#if defined(CONFIG_MPC5xxx)
wdenk21136db2003-07-16 21:53:01 +0000101 unsigned long ipb_clk;
102 unsigned long pci_clk;
103#endif
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200104#if defined(CONFIG_MPC512X)
Grzegorz Bernacki21305af2008-01-11 12:03:43 +0100105 u32 ips_clk;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200106 u32 csb_clk;
John Rigbyd1228c92008-02-26 09:38:14 -0700107 u32 pci_clk;
Rafal Jaworowskid3a02c32007-07-27 14:43:59 +0200108#endif /* CONFIG_MPC512X */
wdenk337f5652004-10-28 00:09:35 +0000109#if defined(CONFIG_MPC8220)
110 unsigned long bExtUart;
111 unsigned long inp_clk;
112 unsigned long pci_clk;
113 unsigned long vco_clk;
114 unsigned long pev_clk;
115 unsigned long flb_clk;
116#endif
wdenk0157ced2002-10-21 17:04:47 +0000117 unsigned long ram_size; /* RAM size */
118 unsigned long reloc_off; /* Relocation Offset */
119 unsigned long reset_status; /* reset status register at boot */
120 unsigned long env_addr; /* Address of Environment struct */
121 unsigned long env_valid; /* Checksum of Environment valid? */
122 unsigned long have_console; /* serial_init() was called */
Jon Loeligerf5ad3782005-07-23 10:37:35 -0500123#if defined(CFG_ALLOC_DPRAM) || defined(CONFIG_CPM2)
wdenk0157ced2002-10-21 17:04:47 +0000124 unsigned int dp_alloc_base;
125 unsigned int dp_alloc_top;
126#endif
Stefan Roese19b77f42007-10-23 11:31:05 +0200127#if defined(CONFIG_4xx)
128 u32 uart_clk;
129#endif /* CONFIG_4xx */
wdenk232fe0b2003-09-02 22:48:03 +0000130#if defined(CFG_GT_6426x)
wdenk0157ced2002-10-21 17:04:47 +0000131 unsigned int mirror_hack[16];
132#endif
wdenke0c812a2005-04-03 15:51:42 +0000133#if defined(CONFIG_A3000) || \
134 defined(CONFIG_HIDDEN_DRAGON) || \
135 defined(CONFIG_MUSENKI) || \
136 defined(CONFIG_SANDPOINT)
wdenk0157ced2002-10-21 17:04:47 +0000137 void * console_addr;
138#endif
wdenk452cfd62002-11-19 11:04:11 +0000139#ifdef CONFIG_AMIGAONEG3SE
140 unsigned long relocaddr; /* Start address of U-Boot in RAM */
141#endif
wdenk0157ced2002-10-21 17:04:47 +0000142#if defined(CONFIG_LCD) || defined(CONFIG_VIDEO)
143 unsigned long fb_base; /* Base address of framebuffer memory */
144#endif
wdenk3aaa67a2003-07-15 21:50:34 +0000145#if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
wdenk9dfa8d12002-12-08 09:53:23 +0000146 unsigned long post_log_word; /* Record POST activities */
wdenkc08f1582003-04-27 22:52:51 +0000147 unsigned long post_init_f_time; /* When post_init_f started */
wdenk9dfa8d12002-12-08 09:53:23 +0000148#endif
wdenk0157ced2002-10-21 17:04:47 +0000149#ifdef CONFIG_BOARD_TYPES
150 unsigned long board_type;
151#endif
wdenkc08f1582003-04-27 22:52:51 +0000152#ifdef CONFIG_MODEM_SUPPORT
153 unsigned long do_mdm_init;
154 unsigned long be_quiet;
155#endif
Stefan Roesef55a22c2007-08-21 16:27:57 +0200156#if defined(CONFIG_LWMON) || defined(CONFIG_LWMON5)
wdenkc08f1582003-04-27 22:52:51 +0000157 unsigned long kbd_status;
wdenk57b2d802003-06-27 21:31:46 +0000158#endif
wdenk874ac262003-07-24 23:38:38 +0000159 void **jt; /* jump table */
wdenk0157ced2002-10-21 17:04:47 +0000160} gd_t;
161
162/*
163 * Global Data Flags
164 */
165#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */
166#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */
wdenk808532a2003-10-10 10:05:42 +0000167#define GD_FLG_SILENT 0x00004 /* Silent mode */
Yuri Tikhonovd773efb2008-02-04 14:11:03 +0100168#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */
wdenk0157ced2002-10-21 17:04:47 +0000169
170#if 1
Wolfgang Denk69c09642008-02-14 22:43:22 +0100171#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
wdenk0157ced2002-10-21 17:04:47 +0000172#else /* We could use plain global data, but the resulting code is bigger */
173#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
174#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
175 gd_t *gd
176#endif
177
178#endif /* __ASM_GBL_DATA_H */