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git01.mediatek.com / filogic / uboot / 16138f9c396302e7b4fd4a5b53a730ca9d3f760a / . / include / configs / CPCI750.h
blob: 1632f374c3c76a3fb86ba24b5ffa1e40a97639df [file] [log] [blame]
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]1/*
2 * (C) Copyright 2001
3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28/*************************************************************************
29 * (c) 2004 esd gmbh Hannover
30 *
31 *
32 * from db64360.h file
33 * by Reinhard Arlt reinhard.arlt@esd-electronics.com
34 *
35 ************************************************************************/
36
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]41/* This define must be before the core.h include */
42#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
43
44#ifndef __ASSEMBLY__
45#include <../board/Marvell/include/core.h>
46#endif
47/*-----------------------------------------------------*/
48
49#include "../board/esd/cpci750/local.h"
50
51/*
52 * High Level Configuration Options
53 * (easy to change)
54 */
55
56#define CONFIG_750FX /* we have a 750FX (override local.h) */
57
58#define CONFIG_CPCI750 1 /* this is an CPCI750 board */
59
60#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600 */
61
62#undef CONFIG_ECC /* enable ECC support */
63
64/* which initialization functions to call for this board */
65#define CONFIG_MISC_INIT_R
66#define CONFIG_BOARD_PRE_INIT
67#define CONFIG_BOARD_EARLY_INIT_F 1
68
69#define CFG_BOARD_NAME "CPCI750"
70#define CONFIG_IDENT_STRING "Marvell 64360 + IBM750FX"
71
72/*#define CFG_HUSH_PARSER*/
Stefan Roeseb7a97c72006-01-18 20:05:34 +0100[diff] [blame]73#define CFG_HUSH_PARSER
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]74
75#define CFG_PROMPT_HUSH_PS2 "> "
76
Stefan Roeseb7a97c72006-01-18 20:05:34 +0100[diff] [blame]77#define CFG_AUTO_COMPLETE 1
78
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]79/* Define which ETH port will be used for connecting the network */
80#define CFG_ETH_PORT ETH_0
81
82/*
83 * The following defines let you select what serial you want to use
84 * for your console driver.
85 *
86 * what to do:
87 * to use the DUART, undef CONFIG_MPSC. If you have hacked a serial
88 * cable onto the second DUART channel, change the CFG_DUART port from 1
89 * to 0 below.
90 *
91 * to use the MPSC, #define CONFIG_MPSC. If you have wired up another
92 * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
93 */
94#define CONFIG_MPSC
95#define CONFIG_MPSC_PORT 0
96
97/* to change the default ethernet port, use this define (options: 0, 1, 2) */
98#define CONFIG_NET_MULTI
99#define MV_ETH_DEVS 1
100#define CONFIG_ETHER_PORT 0
101
102#undef CONFIG_ETHER_PORT_MII /* use RMII */
103
104#define CONFIG_BOOTDELAY 5 /* autoboot disabled */
105
106#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
107
108#define CONFIG_ZERO_BOOTDELAY_CHECK
109
110
111#undef CONFIG_BOOTARGS
112
113/* -----------------------------------------------------------------------------
114 * New bootcommands for Marvell CPCI750 c 2002 Ingo Assmus
115 */
116
117#define CONFIG_IPADDR "192.168.0.185"
118
119#define CONFIG_SERIAL "AA000001"
120#define CONFIG_SERVERIP "10.0.0.79"
121#define CONFIG_ROOTPATH "/export/nfs_cpci750/%s"
122
123#define CONFIG_TESTDRAMDATA y
124#define CONFIG_TESTDRAMADDRESS n
125#define CONFIG_TESETDRAMWALK n
126
127/* ----------------------------------------------------------------------------- */
128
129
130#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
131#define CFG_LOADS_BAUD_CHANGE /* allow baudrate changes */
132
133#undef CONFIG_WATCHDOG /* watchdog disabled */
134#undef CONFIG_ALTIVEC /* undef to disable */
135
136#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
137 CONFIG_BOOTP_BOOTFILESIZE)
138
139
140#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
141 | CFG_CMD_ASKENV \
142 | CFG_CMD_I2C \
143 | CFG_CMD_CACHE \
144 | CFG_CMD_EEPROM \
145 | CFG_CMD_PCI \
146 | CFG_CMD_ELF \
147 | CFG_CMD_DATE \
wdenk07d7e6b2004-12-16 21:44:03 +0000[diff] [blame]148 | CFG_CMD_NET \
149 | CFG_CMD_PING \
150 | CFG_CMD_IDE \
151 | CFG_CMD_FAT \
152 | CFG_CMD_EXT2 \
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]153 )
154
155#define CONFIG_DOS_PARTITION
156
157/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
158#include <cmd_confdefs.h>
159
Stefan Roeseb7a97c72006-01-18 20:05:34 +0100[diff] [blame]160#define CONFIG_USE_CPCIDVI
161
162#ifdef CONFIG_USE_CPCIDVI
163#define CONFIG_VIDEO
164#define CONFIG_VIDEO_CT69000
165#define CONFIG_CFB_CONSOLE
166#define CONFIG_VIDEO_SW_CURSOR
167#define CONFIG_VIDEO_LOGO
168#define CONFIG_I8042_KBD
169#define CFG_ISA_IO 0
170#endif
171
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]172/*
173 * Miscellaneous configurable options
174 */
175#define CFG_I2C_EEPROM_ADDR_LEN 2
176#define CFG_I2C_MULTI_EEPROMS
177#define CFG_I2C_SPEED 80000 /* I2C speed default */
178
179#define CFG_GT_DUAL_CPU /* also for JTAG even with one cpu */
180#define CFG_LONGHELP /* undef to save memory */
181#define CFG_PROMPT "=> " /* Monitor Command Prompt */
182#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
183#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
184#else
185#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
186#endif
187#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
188#define CFG_MAXARGS 16 /* max number of command args */
189#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
190
191/*#define CFG_MEMTEST_START 0x00400000*/ /* memtest works on */
192/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
193/*#define CFG_MEMTEST_END 0x07c00000*/ /* 4 ... 124 MB in DRAM */
194
195/*
196#define CFG_DRAM_TEST
197 * DRAM tests
198 * CFG_DRAM_TEST - enables the following tests.
199 *
200 * CFG_DRAM_TEST_DATA - Enables test for shorted or open data lines
201 * Environment variable 'test_dram_data' must be
202 * set to 'y'.
203 * CFG_DRAM_TEST_DATA - Enables test to verify that each word is uniquely
204 * addressable. Environment variable
205 * 'test_dram_address' must be set to 'y'.
206 * CFG_DRAM_TEST_WALK - Enables test a 64-bit walking ones pattern test.
207 * This test takes about 6 minutes to test 64 MB.
208 * Environment variable 'test_dram_walk' must be
209 * set to 'y'.
210 */
211#define CFG_DRAM_TEST
212#if defined(CFG_DRAM_TEST)
213#define CFG_MEMTEST_START 0x00400000 /* memtest works on */
214/*#define CFG_MEMTEST_END 0x00C00000*/ /* 4 ... 12 MB in DRAM */
215#define CFG_MEMTEST_END 0x07c00000 /* 4 ... 124 MB in DRAM */
216#define CFG_DRAM_TEST_DATA
217#define CFG_DRAM_TEST_ADDRESS
218#define CFG_DRAM_TEST_WALK
219#endif /* CFG_DRAM_TEST */
220
221#define CONFIG_DISPLAY_MEMMAP /* at the end of the bootprocess show the memory map */
222#undef CFG_DISPLAY_DIMM_SPD_CONTENT /* show SPD content during boot */
223
224#define CFG_LOAD_ADDR 0x00300000 /* default load address */
225
226#define CFG_HZ 1000 /* decr freq: 1ms ticks */
227#define CFG_BUS_HZ 133000000 /* 133 MHz (CPU = 5*Bus = 666MHz) */
228#define CFG_BUS_CLK CFG_BUS_HZ
229
230#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
231
232#define CFG_TCLK 133000000
233
234/*#define CFG_750FX_HID0 0x8000c084*/
235#define CFG_750FX_HID0 0x80008484
236#define CFG_750FX_HID1 0x54800000
237#define CFG_750FX_HID2 0x00000000
238
239/*
240 * Low Level Configuration Settings
241 * (address mappings, register initial values, etc.)
242 * You should know what you are doing if you make changes here.
243 */
244
245/*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area
247 */
248
249 /*
250 * When locking data in cache you should point the CFG_INIT_RAM_ADDRESS
251 * To an unused memory region. The stack will remain in cache until RAM
252 * is initialized
253*/
254#undef CFG_INIT_RAM_LOCK
255/* #define CFG_INIT_RAM_ADDR 0x40000000*/ /* unused memory region */
256/* #define CFG_INIT_RAM_ADDR 0xfba00000*/ /* unused memory region */
257#define CFG_INIT_RAM_ADDR 0xf1080000 /* unused memory region */
258#define CFG_INIT_RAM_END 0x1000
259#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
260#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
261
262#define RELOCATE_INTERNAL_RAM_ADDR
263#ifdef RELOCATE_INTERNAL_RAM_ADDR
264/*#define CFG_INTERNAL_RAM_ADDR 0xfba00000*/
265#define CFG_INTERNAL_RAM_ADDR 0xf1080000
266#endif
267
268/*-----------------------------------------------------------------------
269 * Start addresses for the final memory configuration
270 * (Set up by the startup code)
271 * Please note that CFG_SDRAM_BASE _must_ start at 0
272 */
273#define CFG_SDRAM_BASE 0x00000000
274/* Dummies for BAT 4-7 */
275#define CFG_SDRAM1_BASE 0x10000000 /* each 256 MByte */
276#define CFG_SDRAM2_BASE 0x20000000
277#define CFG_SDRAM3_BASE 0x30000000
278#define CFG_SDRAM4_BASE 0x40000000
279#define CFG_RESET_ADDRESS 0xfff00100
280#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
281#define CFG_MONITOR_BASE 0xfff00000
282#define CFG_MALLOC_LEN (128 << 10) /* Reserve 256 kB for malloc */
283
284/*-----------------------------------------------------------------------
285 * FLASH related
286 *----------------------------------------------------------------------*/
287
Stefan Roese16138f92006-02-08 15:54:15 +0100[diff] [blame^]288#define CFG_FLASH_CFI_DRIVER
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]289#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]290#define CFG_FLASH_PROTECTION 1 /* use hardware protection */
291#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
292#define CFG_FLASH_BASE 0xfc000000 /* start of flash banks */
Stefan Roese16138f92006-02-08 15:54:15 +0100[diff] [blame^]293#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
294#define CFG_FLASH_INCREMENT 0x01000000 /* size of flash bank */
295#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
296#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \
297 CFG_FLASH_BASE + 1*CFG_FLASH_INCREMENT, \
298 CFG_FLASH_BASE + 2*CFG_FLASH_INCREMENT, \
299 CFG_FLASH_BASE + 3*CFG_FLASH_INCREMENT }
300#define CFG_FLASH_EMPTY_INFO 1 /* show if bank is empty */
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]301
302/* areas to map different things with the GT in physical space */
303#define CFG_DRAM_BANKS 4
304
305/* What to put in the bats. */
306#define CFG_MISC_REGION_BASE 0xf0000000
307
308/* Peripheral Device section */
309
310/*******************************************************/
311/* We have on the cpci750 Board : */
312/* GT-Chipset Register Area */
313/* GT-Chipset internal SRAM 256k */
314/* SRAM on external device module */
315/* Real time clock on external device module */
316/* dobble UART on external device module */
317/* Data flash on external device module */
318/* Boot flash on external device module */
319/*******************************************************/
320#define CFG_DFL_GT_REGS 0x14000000 /* boot time GT_REGS */
321#define CFG_CPCI750_RESET_ADDR 0x14000000 /* After power on Reset the CPCI750 is here */
322
323#undef MARVEL_STANDARD_CFG
324#ifndef MARVEL_STANDARD_CFG
325/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
326#define CFG_GT_REGS 0xf1000000 /* GT Registers will be mapped here */
327/*#define CFG_DEV_BASE 0xfc000000*/ /* GT Devices CS start here */
328#define CFG_INT_SRAM_BASE 0xf1080000 /* GT offers 256k internal fast SRAM */
329
330#define CFG_BOOT_SPACE 0xff000000 /* BOOT_CS0 flash 0 */
331#define CFG_DEV0_SPACE 0xfc000000 /* DEV_CS0 flash 1 */
332#define CFG_DEV1_SPACE 0xfd000000 /* DEV_CS1 flash 2 */
333#define CFG_DEV2_SPACE 0xfe000000 /* DEV_CS2 flash 3 */
334#define CFG_DEV3_SPACE 0xf0000000 /* DEV_CS3 nvram/can */
335
336#define CFG_BOOT_SIZE _16M /* cpci750 flash 0 */
337#define CFG_DEV0_SIZE _16M /* cpci750 flash 1 */
338#define CFG_DEV1_SIZE _16M /* cpci750 flash 2 */
339#define CFG_DEV2_SIZE _16M /* cpci750 flash 3 */
340#define CFG_DEV3_SIZE _16M /* cpci750 nvram/can */
341
342/*++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++*/
343#endif
344
345/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected by device width */
346#define CFG_DEV0_PAR 0x8FDFFFFF /* 16 bit flash */
347#define CFG_DEV1_PAR 0x8FDFFFFF /* 16 bit flash */
348#define CFG_DEV2_PAR 0x8FDFFFFF /* 16 bit flash */
349#define CFG_DEV3_PAR 0x8FCFFFFF /* nvram/can */
350#define CFG_BOOT_PAR 0x8FDFFFFF /* 16 bit flash */
351
wdenk07d7e6b2004-12-16 21:44:03 +0000[diff] [blame]352 /* c 4 a 8 2 4 1 c */
353 /* 33 22|2222|22 22|111 1|11 11|1 1 | | */
354 /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210 */
355 /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100 */
356 /* 3| 0|.... ..| 2| 4 | 0 | 4 | 8 | 3 | 4 */
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]357
358
359/* MPP Control MV64360 Appendix P P. 632*/
360#define CFG_MPP_CONTROL_0 0x00002222 /* */
361#define CFG_MPP_CONTROL_1 0x11110000 /* */
362#define CFG_MPP_CONTROL_2 0x11111111 /* */
363#define CFG_MPP_CONTROL_3 0x00001111 /* */
364/* #define CFG_SERIAL_PORT_MUX 0x00000102*/ /* */
365
366
367#define CFG_GPP_LEVEL_CONTROL 0xffffffff /* 1111 1111 1111 1111 1111 1111 1111 1111*/
368
369/* setup new config_value for MV64360 DDR-RAM To_do !! */
370/*# define CFG_SDRAM_CONFIG 0xd8e18200*/ /* 0x448 */
371/*# define CFG_SDRAM_CONFIG 0xd8e14400*/ /* 0x1400 */
372 /* GB has high prio.
373 idma has low prio
374 MPSC has low prio
375 pci has low prio 1 and 2
376 cpu has high prio
377 Data DQS pins == eight (DQS[7:0] foe x8 and x16 devices
378 ECC disable
379 non registered DRAM */
380 /* 31:26 25:22 21:20 19 18 17 16 */
381 /* 100001 0000 010 0 0 0 0 */
382 /* refresh_count=0x400
383 phisical interleaving disable
384 virtual interleaving enable */
385 /* 15 14 13:0 */
386 /* 0 1 0x400 */
387# define CFG_SDRAM_CONFIG 0x58200400 /* 0x1400 copied from Dink32 bzw. VxWorks*/
388
389
390/*-----------------------------------------------------------------------
391 * PCI stuff
392 *-----------------------------------------------------------------------
393 */
394
395#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
396#define PCI_HOST_FORCE 1 /* configure as pci host */
397#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
398
399#define CONFIG_PCI /* include pci support */
400#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
401#define CONFIG_PCI_PNP /* do pci plug-and-play */
402#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
403
404/* PCI MEMORY MAP section */
405#define CFG_PCI0_MEM_BASE 0x80000000
406#define CFG_PCI0_MEM_SIZE _128M
407#define CFG_PCI1_MEM_BASE 0x88000000
408#define CFG_PCI1_MEM_SIZE _128M
409
410#define CFG_PCI0_0_MEM_SPACE (CFG_PCI0_MEM_BASE)
411#define CFG_PCI1_0_MEM_SPACE (CFG_PCI1_MEM_BASE)
412
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]413/* PCI I/O MAP section */
414#define CFG_PCI0_IO_BASE 0xfa000000
415#define CFG_PCI0_IO_SIZE _16M
416#define CFG_PCI1_IO_BASE 0xfb000000
417#define CFG_PCI1_IO_SIZE _16M
418
419#define CFG_PCI0_IO_SPACE (CFG_PCI0_IO_BASE)
420#define CFG_PCI0_IO_SPACE_PCI 0x00000000
421#define CFG_PCI1_IO_SPACE (CFG_PCI1_IO_BASE)
422#define CFG_PCI1_IO_SPACE_PCI 0x00000000
423
Stefan Roeseb7a97c72006-01-18 20:05:34 +0100[diff] [blame]424#define CFG_ISA_IO_BASE_ADDRESS (CFG_PCI0_IO_BASE)
425
stroesea9484a92004-12-16 18:05:42 +0000[diff] [blame]426#if defined (CONFIG_750CX)
427#define CFG_PCI_IDSEL 0x0
428#else
429#define CFG_PCI_IDSEL 0x30
430#endif
431
432/*-----------------------------------------------------------------------
433 * IDE/ATA stuff
434 *-----------------------------------------------------------------------
435 */
436#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
437#undef CONFIG_IDE_LED /* no led for ide supported */
438#define CONFIG_IDE_RESET /* no reset for ide supported */
439#define CONFIG_IDE_PREINIT /* check for units */
440
441#define CFG_IDE_MAXBUS 2 /* max. 1 IDE busses */
442#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 1 drives per IDE bus */
443
444#define CFG_ATA_BASE_ADDR 0
445#define CFG_ATA_IDE0_OFFSET 0
446#define CFG_ATA_IDE1_OFFSET 0
447
448#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
449#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
450#define CFG_ATA_ALT_OFFSET 0x0000 /* Offset for alternate registers */
451
452
453/*----------------------------------------------------------------------
454 * Initial BAT mappings
455 */
456
457/* NOTES:
458 * 1) GUARDED and WRITE_THRU not allowed in IBATS
459 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
460 */
461
462/* SDRAM */
463#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
464#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
465#define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
466#define CFG_DBAT0U CFG_IBAT0U
467
468/* init ram */
469#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
470#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
471#define CFG_DBAT1L CFG_IBAT1L
472#define CFG_DBAT1U CFG_IBAT1U
473
474/* PCI0, PCI1 in one BAT */
475#define CFG_IBAT2L BATL_NO_ACCESS
476#define CFG_IBAT2U CFG_DBAT2U
477#define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
478#define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
479
480/* GT regs, bootrom, all the devices, PCI I/O */
481#define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
482#define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
483#define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
484#define CFG_DBAT3U CFG_IBAT3U
485
486/*
487 * 750FX IBAT and DBAT pairs (To_do: define regins for I(D)BAT4 - I(D)BAT7)
488 * IBAT4 and DBAT4
489 * FIXME: ingo disable BATs for Linux Kernel
490 */
491#undef SETUP_HIGH_BATS_FX750 /* don't initialize BATS 4-7 */
492/*#define SETUP_HIGH_BATS_FX750*/ /* initialize BATS 4-7 */
493
494#ifdef SETUP_HIGH_BATS_FX750
495#define CFG_IBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
496#define CFG_IBAT4U (CFG_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
497#define CFG_DBAT4L (CFG_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
498#define CFG_DBAT4U CFG_IBAT4U
499
500/* IBAT5 and DBAT5 */
501#define CFG_IBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
502#define CFG_IBAT5U (CFG_SDRAM2_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
503#define CFG_DBAT5L (CFG_SDRAM2_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
504#define CFG_DBAT5U CFG_IBAT5U
505
506/* IBAT6 and DBAT6 */
507#define CFG_IBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
508#define CFG_IBAT6U (CFG_SDRAM3_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
509#define CFG_DBAT6L (CFG_SDRAM3_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
510#define CFG_DBAT6U CFG_IBAT6U
511
512/* IBAT7 and DBAT7 */
513#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
514#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
515#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
516#define CFG_DBAT7U CFG_IBAT7U
517
518#else /* set em out of range for Linux !!!!!!!!!!! */
519#define CFG_IBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
520#define CFG_IBAT4U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
521#define CFG_DBAT4L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
522#define CFG_DBAT4U CFG_IBAT4U
523
524/* IBAT5 and DBAT5 */
525#define CFG_IBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
526#define CFG_IBAT5U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
527#define CFG_DBAT5L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
528#define CFG_DBAT5U CFG_IBAT4U
529
530/* IBAT6 and DBAT6 */
531#define CFG_IBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
532#define CFG_IBAT6U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
533#define CFG_DBAT6L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
534#define CFG_DBAT6U CFG_IBAT4U
535
536/* IBAT7 and DBAT7 */
537#define CFG_IBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
538#define CFG_IBAT7U (CFG_SDRAM4_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
539#define CFG_DBAT7L (CFG_SDRAM4_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
540#define CFG_DBAT7U CFG_IBAT4U
541
542#endif
543/* FIXME: ingo end: disable BATs for Linux Kernel */
544
545/* I2C addresses for the two DIMM SPD chips */
546#define DIMM0_I2C_ADDR 0x51
547#define DIMM1_I2C_ADDR 0x52
548
549/*
550 * For booting Linux, the board info and command line data
551 * have to be in the first 8 MB of memory, since this is
552 * the maximum mapped by the Linux kernel during initialization.
553 */
554#define CFG_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
555
556/*-----------------------------------------------------------------------
557 * FLASH organization
558 */
559#define CFG_BOOT_FLASH_WIDTH 2 /* 16 bit */
560
561#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
562#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
563#define CFG_FLASH_LOCK_TOUT 500 /* Timeout for Flash Lock (in ms) */
564
565#if 0
566#define CFG_ENV_IS_IN_FLASH 0
567#define CFG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
568#define CFG_ENV_SECT_SIZE 0x10000
569#define CFG_ENV_ADDR 0xFFF78000 /* Marvell 8-Bit Bootflash last sector */
570/* #define CFG_ENV_ADDR (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE) */
571#endif
572
573#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
574#define CFG_EEPROM_PAGE_WRITE_BITS 5
575#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
576#define CFG_I2C_EEPROM_ADDR 0x050
577#define CFG_ENV_OFFSET 0x200 /* environment starts at the beginning of the EEPROM */
578#define CFG_ENV_SIZE 0x600 /* 2048 bytes may be used for env vars*/
579
580#define CFG_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
581#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
582#define CFG_VXWORKS_MAC_PTR (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-0x40)
583
584/*-----------------------------------------------------------------------
585 * Cache Configuration
586 */
587#define CFG_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
588#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
589#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
590#endif
591
592/*-----------------------------------------------------------------------
593 * L2CR setup -- make sure this is right for your board!
594 * look in include/mpc74xx.h for the defines used here
595 */
596
597/*#define CFG_L2*/
598#undef CFG_L2
599
600/* #ifdef CONFIG_750CX*/
601#if defined (CONFIG_750CX) || defined (CONFIG_750FX)
602#define L2_INIT 0
603#else
604#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
605 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
606#endif
607
608#define L2_ENABLE (L2_INIT | L2CR_L2E)
609
610/*
611 * Internal Definitions
612 *
613 * Boot Flags
614 */
615#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
616#define BOOTFLAG_WARM 0x02 /* Software reboot */
617
618#define CFG_BOARD_ASM_INIT 1
619
620#endif /* __CONFIG_H */