Paul Barker | bdc193d | 2024-02-27 20:40:33 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2023 Renesas Electronics Corporation |
| 4 | */ |
| 5 | |
| 6 | #include <dm.h> |
| 7 | #include <power/pmic.h> |
| 8 | #include <sysreset.h> |
| 9 | |
| 10 | #define RAA215300_REG_SWRESET 0x6D |
| 11 | #define RAA215300_COLD_RESET BIT(0) |
| 12 | #define RAA215300_WARM_RESET BIT(1) |
| 13 | |
| 14 | static int raa215300_sysreset_request(struct udevice *dev, enum sysreset_t type) |
| 15 | { |
| 16 | struct udevice *pmic = dev_get_parent(dev); |
| 17 | int ret; |
| 18 | u8 val; |
| 19 | |
| 20 | /* |
| 21 | * The RAA215300 documentation names the available reset types |
| 22 | * differently to u-boot: |
| 23 | * |
| 24 | * - A "warm" reset via the RAA215300 PMIC will fully reset the SoC |
| 25 | * (CPU & GPIOs), so this corresponds to SYSRESET_COLD. |
| 26 | * |
| 27 | * - A "cold" reset via the RAA215300 PMIC will cycle all power supply |
| 28 | * rails, so this corresponds to SYSRESET_POWER. |
| 29 | */ |
| 30 | switch (type) { |
| 31 | case SYSRESET_COLD: |
| 32 | val = RAA215300_WARM_RESET; |
| 33 | break; |
| 34 | |
| 35 | case SYSRESET_POWER: |
| 36 | val = RAA215300_COLD_RESET; |
| 37 | break; |
| 38 | |
| 39 | default: |
| 40 | return -EPROTONOSUPPORT; |
| 41 | } |
| 42 | |
| 43 | ret = pmic_reg_write(pmic, RAA215300_REG_SWRESET, val); |
| 44 | if (ret) |
| 45 | return ret; |
| 46 | |
| 47 | return -EINPROGRESS; |
| 48 | } |
| 49 | |
| 50 | static struct sysreset_ops raa215300_sysreset_ops = { |
| 51 | .request = raa215300_sysreset_request, |
| 52 | }; |
| 53 | |
| 54 | U_BOOT_DRIVER(raa215300_sysreset) = { |
| 55 | .name = "raa215300_sysreset", |
| 56 | .id = UCLASS_SYSRESET, |
| 57 | .ops = &raa215300_sysreset_ops, |
| 58 | }; |