Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2 | /* |
| 3 | * R8A77995 processor support - PFC hardware block. |
| 4 | * |
| 5 | * Copyright (C) 2017 Renesas Electronics Corp. |
| 6 | * |
Marek Vasut | 0e8e989 | 2021-04-26 22:04:11 +0200 | [diff] [blame] | 7 | * This file is based on the drivers/pinctrl/renesas/pfc-r8a7796.c |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 8 | * |
| 9 | * R-Car Gen3 processor support - PFC hardware block. |
| 10 | * |
| 11 | * Copyright (C) 2015 Renesas Electronics Corporation |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 12 | */ |
| 13 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 14 | #include <dm.h> |
| 15 | #include <errno.h> |
| 16 | #include <dm/pinctrl.h> |
| 17 | #include <linux/kernel.h> |
| 18 | |
| 19 | #include "sh_pfc.h" |
| 20 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 21 | #define CPU_ALL_GP(fn, sfx) \ |
| 22 | PORT_GP_CFG_9(0, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 23 | PORT_GP_CFG_32(1, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 24 | PORT_GP_CFG_32(2, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 25 | PORT_GP_CFG_10(3, fn, sfx, SH_PFC_PIN_CFG_IO_VOLTAGE_18_33 | SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 26 | PORT_GP_CFG_32(4, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 27 | PORT_GP_CFG_21(5, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 28 | PORT_GP_CFG_14(6, fn, sfx, SH_PFC_PIN_CFG_PULL_UP_DOWN) |
| 29 | |
| 30 | #define CPU_ALL_NOGP(fn) \ |
| 31 | PIN_NOGP_CFG(DU_DOTCLKIN0, "DU_DOTCLKIN0", fn, SH_PFC_PIN_CFG_PULL_DOWN), \ |
| 32 | PIN_NOGP_CFG(FSCLKST_N, "FSCLKST#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 33 | PIN_NOGP_CFG(MLB_REF, "MLB_REF", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 34 | PIN_NOGP_CFG(PRESETOUT_N, "PRESETOUT#", fn, SH_PFC_PIN_CFG_PULL_UP_DOWN), \ |
| 35 | PIN_NOGP_CFG(TCK, "TCK", fn, SH_PFC_PIN_CFG_PULL_UP), \ |
| 36 | PIN_NOGP_CFG(TDI, "TDI", fn, SH_PFC_PIN_CFG_PULL_UP), \ |
| 37 | PIN_NOGP_CFG(TMS, "TMS", fn, SH_PFC_PIN_CFG_PULL_UP), \ |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 38 | PIN_NOGP_CFG(TRST_N, "TRST#", fn, SH_PFC_PIN_CFG_PULL_UP), \ |
| 39 | PIN_NOGP_CFG(VDDQ_AVB0, "VDDQ_AVB0", fn, SH_PFC_PIN_CFG_IO_VOLTAGE_25_33) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 40 | |
| 41 | /* |
| 42 | * F_() : just information |
| 43 | * FM() : macro for FN_xxx / xxx_MARK |
| 44 | */ |
| 45 | |
| 46 | /* GPSR0 */ |
| 47 | #define GPSR0_8 F_(MLB_SIG, IP0_27_24) |
| 48 | #define GPSR0_7 F_(MLB_DAT, IP0_23_20) |
| 49 | #define GPSR0_6 F_(MLB_CLK, IP0_19_16) |
| 50 | #define GPSR0_5 F_(MSIOF2_RXD, IP0_15_12) |
| 51 | #define GPSR0_4 F_(MSIOF2_TXD, IP0_11_8) |
| 52 | #define GPSR0_3 F_(MSIOF2_SCK, IP0_7_4) |
| 53 | #define GPSR0_2 F_(IRQ0_A, IP0_3_0) |
| 54 | #define GPSR0_1 FM(USB0_OVC) |
| 55 | #define GPSR0_0 FM(USB0_PWEN) |
| 56 | |
| 57 | /* GPSR1 */ |
| 58 | #define GPSR1_31 F_(QPOLB, IP4_27_24) |
| 59 | #define GPSR1_30 F_(QPOLA, IP4_23_20) |
| 60 | #define GPSR1_29 F_(DU_CDE, IP4_19_16) |
| 61 | #define GPSR1_28 F_(DU_DISP_CDE, IP4_15_12) |
| 62 | #define GPSR1_27 F_(DU_DISP, IP4_11_8) |
| 63 | #define GPSR1_26 F_(DU_VSYNC, IP4_7_4) |
| 64 | #define GPSR1_25 F_(DU_HSYNC, IP4_3_0) |
| 65 | #define GPSR1_24 F_(DU_DOTCLKOUT0, IP3_31_28) |
| 66 | #define GPSR1_23 F_(DU_DR7, IP3_27_24) |
| 67 | #define GPSR1_22 F_(DU_DR6, IP3_23_20) |
| 68 | #define GPSR1_21 F_(DU_DR5, IP3_19_16) |
| 69 | #define GPSR1_20 F_(DU_DR4, IP3_15_12) |
| 70 | #define GPSR1_19 F_(DU_DR3, IP3_11_8) |
| 71 | #define GPSR1_18 F_(DU_DR2, IP3_7_4) |
| 72 | #define GPSR1_17 F_(DU_DR1, IP3_3_0) |
| 73 | #define GPSR1_16 F_(DU_DR0, IP2_31_28) |
| 74 | #define GPSR1_15 F_(DU_DG7, IP2_27_24) |
| 75 | #define GPSR1_14 F_(DU_DG6, IP2_23_20) |
| 76 | #define GPSR1_13 F_(DU_DG5, IP2_19_16) |
| 77 | #define GPSR1_12 F_(DU_DG4, IP2_15_12) |
| 78 | #define GPSR1_11 F_(DU_DG3, IP2_11_8) |
| 79 | #define GPSR1_10 F_(DU_DG2, IP2_7_4) |
| 80 | #define GPSR1_9 F_(DU_DG1, IP2_3_0) |
| 81 | #define GPSR1_8 F_(DU_DG0, IP1_31_28) |
| 82 | #define GPSR1_7 F_(DU_DB7, IP1_27_24) |
| 83 | #define GPSR1_6 F_(DU_DB6, IP1_23_20) |
| 84 | #define GPSR1_5 F_(DU_DB5, IP1_19_16) |
| 85 | #define GPSR1_4 F_(DU_DB4, IP1_15_12) |
| 86 | #define GPSR1_3 F_(DU_DB3, IP1_11_8) |
| 87 | #define GPSR1_2 F_(DU_DB2, IP1_7_4) |
| 88 | #define GPSR1_1 F_(DU_DB1, IP1_3_0) |
| 89 | #define GPSR1_0 F_(DU_DB0, IP0_31_28) |
| 90 | |
| 91 | /* GPSR2 */ |
| 92 | #define GPSR2_31 F_(NFCE_N, IP8_19_16) |
| 93 | #define GPSR2_30 F_(NFCLE, IP8_15_12) |
| 94 | #define GPSR2_29 F_(NFALE, IP8_11_8) |
| 95 | #define GPSR2_28 F_(VI4_CLKENB, IP8_7_4) |
| 96 | #define GPSR2_27 F_(VI4_FIELD, IP8_3_0) |
| 97 | #define GPSR2_26 F_(VI4_HSYNC_N, IP7_31_28) |
| 98 | #define GPSR2_25 F_(VI4_VSYNC_N, IP7_27_24) |
| 99 | #define GPSR2_24 F_(VI4_DATA23, IP7_23_20) |
| 100 | #define GPSR2_23 F_(VI4_DATA22, IP7_19_16) |
| 101 | #define GPSR2_22 F_(VI4_DATA21, IP7_15_12) |
| 102 | #define GPSR2_21 F_(VI4_DATA20, IP7_11_8) |
| 103 | #define GPSR2_20 F_(VI4_DATA19, IP7_7_4) |
| 104 | #define GPSR2_19 F_(VI4_DATA18, IP7_3_0) |
| 105 | #define GPSR2_18 F_(VI4_DATA17, IP6_31_28) |
| 106 | #define GPSR2_17 F_(VI4_DATA16, IP6_27_24) |
| 107 | #define GPSR2_16 F_(VI4_DATA15, IP6_23_20) |
| 108 | #define GPSR2_15 F_(VI4_DATA14, IP6_19_16) |
| 109 | #define GPSR2_14 F_(VI4_DATA13, IP6_15_12) |
| 110 | #define GPSR2_13 F_(VI4_DATA12, IP6_11_8) |
| 111 | #define GPSR2_12 F_(VI4_DATA11, IP6_7_4) |
| 112 | #define GPSR2_11 F_(VI4_DATA10, IP6_3_0) |
| 113 | #define GPSR2_10 F_(VI4_DATA9, IP5_31_28) |
| 114 | #define GPSR2_9 F_(VI4_DATA8, IP5_27_24) |
| 115 | #define GPSR2_8 F_(VI4_DATA7, IP5_23_20) |
| 116 | #define GPSR2_7 F_(VI4_DATA6, IP5_19_16) |
| 117 | #define GPSR2_6 F_(VI4_DATA5, IP5_15_12) |
| 118 | #define GPSR2_5 FM(VI4_DATA4) |
| 119 | #define GPSR2_4 F_(VI4_DATA3, IP5_11_8) |
| 120 | #define GPSR2_3 F_(VI4_DATA2, IP5_7_4) |
| 121 | #define GPSR2_2 F_(VI4_DATA1, IP5_3_0) |
| 122 | #define GPSR2_1 F_(VI4_DATA0, IP4_31_28) |
| 123 | #define GPSR2_0 FM(VI4_CLK) |
| 124 | |
| 125 | /* GPSR3 */ |
| 126 | #define GPSR3_9 F_(NFDATA7, IP9_31_28) |
| 127 | #define GPSR3_8 F_(NFDATA6, IP9_27_24) |
| 128 | #define GPSR3_7 F_(NFDATA5, IP9_23_20) |
| 129 | #define GPSR3_6 F_(NFDATA4, IP9_19_16) |
| 130 | #define GPSR3_5 F_(NFDATA3, IP9_15_12) |
| 131 | #define GPSR3_4 F_(NFDATA2, IP9_11_8) |
| 132 | #define GPSR3_3 F_(NFDATA1, IP9_7_4) |
| 133 | #define GPSR3_2 F_(NFDATA0, IP9_3_0) |
| 134 | #define GPSR3_1 F_(NFWE_N, IP8_31_28) |
| 135 | #define GPSR3_0 F_(NFRE_N, IP8_27_24) |
| 136 | |
| 137 | /* GPSR4 */ |
| 138 | #define GPSR4_31 F_(CAN0_RX_A, IP12_27_24) |
| 139 | #define GPSR4_30 F_(CAN1_TX_A, IP13_7_4) |
| 140 | #define GPSR4_29 F_(CAN1_RX_A, IP13_3_0) |
| 141 | #define GPSR4_28 F_(CAN0_TX_A, IP12_31_28) |
| 142 | #define GPSR4_27 FM(TX2) |
| 143 | #define GPSR4_26 FM(RX2) |
| 144 | #define GPSR4_25 F_(SCK2, IP12_11_8) |
| 145 | #define GPSR4_24 F_(TX1_A, IP12_7_4) |
| 146 | #define GPSR4_23 F_(RX1_A, IP12_3_0) |
| 147 | #define GPSR4_22 F_(SCK1_A, IP11_31_28) |
| 148 | #define GPSR4_21 F_(TX0_A, IP11_27_24) |
| 149 | #define GPSR4_20 F_(RX0_A, IP11_23_20) |
| 150 | #define GPSR4_19 F_(SCK0_A, IP11_19_16) |
| 151 | #define GPSR4_18 F_(MSIOF1_RXD, IP11_15_12) |
| 152 | #define GPSR4_17 F_(MSIOF1_TXD, IP11_11_8) |
| 153 | #define GPSR4_16 F_(MSIOF1_SCK, IP11_7_4) |
| 154 | #define GPSR4_15 FM(MSIOF0_RXD) |
| 155 | #define GPSR4_14 FM(MSIOF0_TXD) |
| 156 | #define GPSR4_13 FM(MSIOF0_SYNC) |
| 157 | #define GPSR4_12 FM(MSIOF0_SCK) |
| 158 | #define GPSR4_11 F_(SDA1, IP11_3_0) |
| 159 | #define GPSR4_10 F_(SCL1, IP10_31_28) |
| 160 | #define GPSR4_9 FM(SDA0) |
| 161 | #define GPSR4_8 FM(SCL0) |
| 162 | #define GPSR4_7 F_(SSI_WS4_A, IP10_27_24) |
| 163 | #define GPSR4_6 F_(SSI_SDATA4_A, IP10_23_20) |
| 164 | #define GPSR4_5 F_(SSI_SCK4_A, IP10_19_16) |
| 165 | #define GPSR4_4 F_(SSI_WS34, IP10_15_12) |
| 166 | #define GPSR4_3 F_(SSI_SDATA3, IP10_11_8) |
| 167 | #define GPSR4_2 F_(SSI_SCK34, IP10_7_4) |
| 168 | #define GPSR4_1 F_(AUDIO_CLKA, IP10_3_0) |
| 169 | #define GPSR4_0 F_(NFRB_N, IP8_23_20) |
| 170 | |
| 171 | /* GPSR5 */ |
| 172 | #define GPSR5_20 FM(AVB0_LINK) |
| 173 | #define GPSR5_19 FM(AVB0_PHY_INT) |
| 174 | #define GPSR5_18 FM(AVB0_MAGIC) |
| 175 | #define GPSR5_17 FM(AVB0_MDC) |
| 176 | #define GPSR5_16 FM(AVB0_MDIO) |
| 177 | #define GPSR5_15 FM(AVB0_TXCREFCLK) |
| 178 | #define GPSR5_14 FM(AVB0_TD3) |
| 179 | #define GPSR5_13 FM(AVB0_TD2) |
| 180 | #define GPSR5_12 FM(AVB0_TD1) |
| 181 | #define GPSR5_11 FM(AVB0_TD0) |
| 182 | #define GPSR5_10 FM(AVB0_TXC) |
| 183 | #define GPSR5_9 FM(AVB0_TX_CTL) |
| 184 | #define GPSR5_8 FM(AVB0_RD3) |
| 185 | #define GPSR5_7 FM(AVB0_RD2) |
| 186 | #define GPSR5_6 FM(AVB0_RD1) |
| 187 | #define GPSR5_5 FM(AVB0_RD0) |
| 188 | #define GPSR5_4 FM(AVB0_RXC) |
| 189 | #define GPSR5_3 FM(AVB0_RX_CTL) |
| 190 | #define GPSR5_2 F_(CAN_CLK, IP12_23_20) |
| 191 | #define GPSR5_1 F_(TPU0TO1_A, IP12_19_16) |
| 192 | #define GPSR5_0 F_(TPU0TO0_A, IP12_15_12) |
| 193 | |
| 194 | /* GPSR6 */ |
| 195 | #define GPSR6_13 FM(RPC_INT_N) |
| 196 | #define GPSR6_12 FM(RPC_RESET_N) |
| 197 | #define GPSR6_11 FM(QSPI1_SSL) |
| 198 | #define GPSR6_10 FM(QSPI1_IO3) |
| 199 | #define GPSR6_9 FM(QSPI1_IO2) |
| 200 | #define GPSR6_8 FM(QSPI1_MISO_IO1) |
| 201 | #define GPSR6_7 FM(QSPI1_MOSI_IO0) |
| 202 | #define GPSR6_6 FM(QSPI1_SPCLK) |
| 203 | #define GPSR6_5 FM(QSPI0_SSL) |
| 204 | #define GPSR6_4 FM(QSPI0_IO3) |
| 205 | #define GPSR6_3 FM(QSPI0_IO2) |
| 206 | #define GPSR6_2 FM(QSPI0_MISO_IO1) |
| 207 | #define GPSR6_1 FM(QSPI0_MOSI_IO0) |
| 208 | #define GPSR6_0 FM(QSPI0_SPCLK) |
| 209 | |
| 210 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 211 | #define IP0_3_0 FM(IRQ0_A) FM(MSIOF2_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 212 | #define IP0_7_4 FM(MSIOF2_SCK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 213 | #define IP0_11_8 FM(MSIOF2_TXD) FM(SCL3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 214 | #define IP0_15_12 FM(MSIOF2_RXD) FM(SDA3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 215 | #define IP0_19_16 FM(MLB_CLK) FM(MSIOF2_SYNC_A) FM(SCK5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 216 | #define IP0_23_20 FM(MLB_DAT) FM(MSIOF2_SS1) FM(RX5_A) FM(SCL3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 217 | #define IP0_27_24 FM(MLB_SIG) FM(MSIOF2_SS2) FM(TX5_A) FM(SDA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 218 | #define IP0_31_28 FM(DU_DB0) FM(LCDOUT0) FM(MSIOF3_TXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 219 | #define IP1_3_0 FM(DU_DB1) FM(LCDOUT1) FM(MSIOF3_RXD_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 220 | #define IP1_7_4 FM(DU_DB2) FM(LCDOUT2) FM(IRQ0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 221 | #define IP1_11_8 FM(DU_DB3) FM(LCDOUT3) FM(SCK5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 222 | #define IP1_15_12 FM(DU_DB4) FM(LCDOUT4) FM(RX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 223 | #define IP1_19_16 FM(DU_DB5) FM(LCDOUT5) FM(TX5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 224 | #define IP1_23_20 FM(DU_DB6) FM(LCDOUT6) FM(MSIOF3_SS1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 225 | #define IP1_27_24 FM(DU_DB7) FM(LCDOUT7) FM(MSIOF3_SS2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 226 | #define IP1_31_28 FM(DU_DG0) FM(LCDOUT8) FM(MSIOF3_SCK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 227 | #define IP2_3_0 FM(DU_DG1) FM(LCDOUT9) FM(MSIOF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 228 | #define IP2_7_4 FM(DU_DG2) FM(LCDOUT10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 229 | #define IP2_11_8 FM(DU_DG3) FM(LCDOUT11) FM(IRQ1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 230 | #define IP2_15_12 FM(DU_DG4) FM(LCDOUT12) FM(HSCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 231 | #define IP2_19_16 FM(DU_DG5) FM(LCDOUT13) FM(HTX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 232 | #define IP2_23_20 FM(DU_DG6) FM(LCDOUT14) FM(HRX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 233 | #define IP2_27_24 FM(DU_DG7) FM(LCDOUT15) FM(SCK4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 234 | #define IP2_31_28 FM(DU_DR0) FM(LCDOUT16) FM(RX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 235 | #define IP3_3_0 FM(DU_DR1) FM(LCDOUT17) FM(TX4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 236 | #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 237 | #define IP3_11_8 FM(DU_DR3) FM(LCDOUT19) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 238 | #define IP3_15_12 FM(DU_DR4) FM(LCDOUT20) FM(TCLK2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 239 | #define IP3_19_16 FM(DU_DR5) FM(LCDOUT21) FM(NMI) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 240 | #define IP3_23_20 FM(DU_DR6) FM(LCDOUT22) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 241 | #define IP3_27_24 FM(DU_DR7) FM(LCDOUT23) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 242 | #define IP3_31_28 FM(DU_DOTCLKOUT0) FM(QCLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 243 | |
| 244 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
| 245 | #define IP4_3_0 FM(DU_HSYNC) FM(QSTH_QHS) FM(IRQ3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 246 | #define IP4_7_4 FM(DU_VSYNC) FM(QSTVA_QVS) FM(IRQ4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 247 | #define IP4_11_8 FM(DU_DISP) FM(QSTVB_QVE) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 248 | #define IP4_15_12 FM(DU_DISP_CDE) FM(QCPV_QDE) FM(IRQ2_B) FM(DU_DOTCLKIN1)F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 249 | #define IP4_19_16 FM(DU_CDE) FM(QSTB_QHE) FM(SCK3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 250 | #define IP4_23_20 FM(QPOLA) F_(0, 0) FM(RX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 251 | #define IP4_27_24 FM(QPOLB) F_(0, 0) FM(TX3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 252 | #define IP4_31_28 FM(VI4_DATA0) FM(PWM0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 253 | #define IP5_3_0 FM(VI4_DATA1) FM(PWM1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 254 | #define IP5_7_4 FM(VI4_DATA2) FM(PWM2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 255 | #define IP5_11_8 FM(VI4_DATA3) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 256 | #define IP5_15_12 FM(VI4_DATA5) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 257 | #define IP5_19_16 FM(VI4_DATA6) FM(IRQ2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 258 | #define IP5_23_20 FM(VI4_DATA7) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 259 | #define IP5_27_24 FM(VI4_DATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 260 | #define IP5_31_28 FM(VI4_DATA9) FM(MSIOF3_SS2_A) FM(IRQ1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 261 | #define IP6_3_0 FM(VI4_DATA10) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 262 | #define IP6_7_4 FM(VI4_DATA11) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 263 | #define IP6_11_8 FM(VI4_DATA12) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 264 | #define IP6_15_12 FM(VI4_DATA13) FM(MSIOF3_SS1_A) FM(HCTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 265 | #define IP6_19_16 FM(VI4_DATA14) FM(SSI_SCK4_B) FM(HRTS3_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 266 | #define IP6_23_20 FM(VI4_DATA15) FM(SSI_SDATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 267 | #define IP6_27_24 FM(VI4_DATA16) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 268 | #define IP6_31_28 FM(VI4_DATA17) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 269 | #define IP7_3_0 FM(VI4_DATA18) FM(HSCK3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 270 | #define IP7_7_4 FM(VI4_DATA19) FM(SSI_WS4_B) F_(0, 0) F_(0, 0) FM(NFDATA15) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 271 | #define IP7_11_8 FM(VI4_DATA20) FM(MSIOF3_SYNC_A) F_(0, 0) F_(0, 0) FM(NFDATA14) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 272 | #define IP7_15_12 FM(VI4_DATA21) FM(MSIOF3_TXD_A) F_(0, 0) F_(0, 0) FM(NFDATA13) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 273 | #define IP7_19_16 FM(VI4_DATA22) FM(MSIOF3_RXD_A) F_(0, 0) F_(0, 0) FM(NFDATA12) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 274 | #define IP7_23_20 FM(VI4_DATA23) FM(MSIOF3_SCK_A) F_(0, 0) F_(0, 0) FM(NFDATA11) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 275 | #define IP7_27_24 FM(VI4_VSYNC_N) FM(SCK1_B) F_(0, 0) F_(0, 0) FM(NFDATA10) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 276 | #define IP7_31_28 FM(VI4_HSYNC_N) FM(RX1_B) F_(0, 0) F_(0, 0) FM(NFDATA9) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 277 | |
| 278 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
| 279 | #define IP8_3_0 FM(VI4_FIELD) FM(AUDIO_CLKB) FM(IRQ5_A) FM(SCIF_CLK) FM(NFDATA8) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 280 | #define IP8_7_4 FM(VI4_CLKENB) FM(TX1_B) F_(0, 0) F_(0, 0) FM(NFWP_N) FM(DVC_MUTE_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 281 | #define IP8_11_8 FM(NFALE) FM(SCL2_B) FM(IRQ3_B) FM(PWM0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 282 | #define IP8_15_12 FM(NFCLE) FM(SDA2_B) FM(SCK3_A) FM(PWM1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 283 | #define IP8_19_16 FM(NFCE_N) F_(0, 0) FM(RX3_A) FM(PWM2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 284 | #define IP8_23_20 FM(NFRB_N) F_(0, 0) FM(TX3_A) FM(PWM3_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 285 | #define IP8_27_24 FM(NFRE_N) FM(MMC_CMD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 286 | #define IP8_31_28 FM(NFWE_N) FM(MMC_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 287 | #define IP9_3_0 FM(NFDATA0) FM(MMC_D0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 288 | #define IP9_7_4 FM(NFDATA1) FM(MMC_D1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 289 | #define IP9_11_8 FM(NFDATA2) FM(MMC_D2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 290 | #define IP9_15_12 FM(NFDATA3) FM(MMC_D3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 291 | #define IP9_19_16 FM(NFDATA4) FM(MMC_D4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 292 | #define IP9_23_20 FM(NFDATA5) FM(MMC_D5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 293 | #define IP9_27_24 FM(NFDATA6) FM(MMC_D6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 294 | #define IP9_31_28 FM(NFDATA7) FM(MMC_D7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 295 | #define IP10_3_0 FM(AUDIO_CLKA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(DVC_MUTE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 296 | #define IP10_7_4 FM(SSI_SCK34) FM(FSO_CFE_0_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 297 | #define IP10_11_8 FM(SSI_SDATA3) FM(FSO_CFE_1_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 298 | #define IP10_15_12 FM(SSI_WS34) FM(FSO_TOE_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 299 | #define IP10_19_16 FM(SSI_SCK4_A) FM(HSCK0) FM(AUDIO_CLKOUT) FM(CAN0_RX_B) FM(IRQ4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 300 | #define IP10_23_20 FM(SSI_SDATA4_A) FM(HTX0) FM(SCL2_A) FM(CAN1_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 301 | #define IP10_27_24 FM(SSI_WS4_A) FM(HRX0) FM(SDA2_A) FM(CAN1_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 302 | #define IP10_31_28 FM(SCL1) FM(CTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 303 | #define IP11_3_0 FM(SDA1) FM(RTS1_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 304 | #define IP11_7_4 FM(MSIOF1_SCK) FM(AVB0_AVTP_PPS_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 305 | #define IP11_11_8 FM(MSIOF1_TXD) FM(AVB0_AVTP_CAPTURE_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 306 | #define IP11_15_12 FM(MSIOF1_RXD) FM(AVB0_AVTP_MATCH_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 307 | #define IP11_19_16 FM(SCK0_A) FM(MSIOF1_SYNC) FM(FSO_CFE_0_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 308 | #define IP11_23_20 FM(RX0_A) FM(MSIOF0_SS1) FM(FSO_CFE_1_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 309 | #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 310 | #define IP11_31_28 FM(SCK1_A) FM(MSIOF1_SS2) FM(TPU0TO2_B) FM(CAN0_TX_B) FM(AUDIO_CLKOUT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 311 | |
| 312 | /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 - F */ |
| 313 | #define IP12_3_0 FM(RX1_A) FM(CTS0_N) FM(TPU0TO0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 314 | #define IP12_7_4 FM(TX1_A) FM(RTS0_N) FM(TPU0TO1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 315 | #define IP12_11_8 FM(SCK2) FM(MSIOF1_SS1) FM(TPU0TO3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 316 | #define IP12_15_12 FM(TPU0TO0_A) FM(AVB0_AVTP_CAPTURE_A) FM(HCTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 317 | #define IP12_19_16 FM(TPU0TO1_A) FM(AVB0_AVTP_MATCH_A) FM(HRTS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 318 | #define IP12_23_20 FM(CAN_CLK) FM(AVB0_AVTP_PPS_A) FM(SCK0_B) FM(IRQ5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 319 | #define IP12_27_24 FM(CAN0_RX_A) FM(CANFD0_RX) FM(RX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 320 | #define IP12_31_28 FM(CAN0_TX_A) FM(CANFD0_TX) FM(TX0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 321 | #define IP13_3_0 FM(CAN1_RX_A) FM(CANFD1_RX) FM(TPU0TO2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 322 | #define IP13_7_4 FM(CAN1_TX_A) FM(CANFD1_TX) FM(TPU0TO3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) |
| 323 | |
| 324 | #define PINMUX_GPSR \ |
| 325 | \ |
| 326 | GPSR1_31 GPSR2_31 GPSR4_31 \ |
| 327 | GPSR1_30 GPSR2_30 GPSR4_30 \ |
| 328 | GPSR1_29 GPSR2_29 GPSR4_29 \ |
| 329 | GPSR1_28 GPSR2_28 GPSR4_28 \ |
| 330 | GPSR1_27 GPSR2_27 GPSR4_27 \ |
| 331 | GPSR1_26 GPSR2_26 GPSR4_26 \ |
| 332 | GPSR1_25 GPSR2_25 GPSR4_25 \ |
| 333 | GPSR1_24 GPSR2_24 GPSR4_24 \ |
| 334 | GPSR1_23 GPSR2_23 GPSR4_23 \ |
| 335 | GPSR1_22 GPSR2_22 GPSR4_22 \ |
| 336 | GPSR1_21 GPSR2_21 GPSR4_21 \ |
| 337 | GPSR1_20 GPSR2_20 GPSR4_20 GPSR5_20 \ |
| 338 | GPSR1_19 GPSR2_19 GPSR4_19 GPSR5_19 \ |
| 339 | GPSR1_18 GPSR2_18 GPSR4_18 GPSR5_18 \ |
| 340 | GPSR1_17 GPSR2_17 GPSR4_17 GPSR5_17 \ |
| 341 | GPSR1_16 GPSR2_16 GPSR4_16 GPSR5_16 \ |
| 342 | GPSR1_15 GPSR2_15 GPSR4_15 GPSR5_15 \ |
| 343 | GPSR1_14 GPSR2_14 GPSR4_14 GPSR5_14 \ |
| 344 | GPSR1_13 GPSR2_13 GPSR4_13 GPSR5_13 GPSR6_13 \ |
| 345 | GPSR1_12 GPSR2_12 GPSR4_12 GPSR5_12 GPSR6_12 \ |
| 346 | GPSR1_11 GPSR2_11 GPSR4_11 GPSR5_11 GPSR6_11 \ |
| 347 | GPSR1_10 GPSR2_10 GPSR4_10 GPSR5_10 GPSR6_10 \ |
| 348 | GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \ |
| 349 | GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \ |
| 350 | GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \ |
| 351 | GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \ |
| 352 | GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \ |
| 353 | GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \ |
| 354 | GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 \ |
| 355 | GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 \ |
| 356 | GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 \ |
| 357 | GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 |
| 358 | |
| 359 | #define PINMUX_IPSR \ |
| 360 | \ |
| 361 | FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \ |
| 362 | FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \ |
| 363 | FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \ |
| 364 | FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \ |
| 365 | FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \ |
| 366 | FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \ |
| 367 | FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \ |
| 368 | FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \ |
| 369 | \ |
| 370 | FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \ |
| 371 | FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \ |
| 372 | FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \ |
| 373 | FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \ |
| 374 | FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \ |
| 375 | FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \ |
| 376 | FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \ |
| 377 | FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \ |
| 378 | \ |
| 379 | FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \ |
| 380 | FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \ |
| 381 | FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \ |
| 382 | FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \ |
| 383 | FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \ |
| 384 | FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \ |
| 385 | FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \ |
| 386 | FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \ |
| 387 | \ |
| 388 | FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 \ |
| 389 | FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 \ |
| 390 | FM(IP12_11_8) IP12_11_8 \ |
| 391 | FM(IP12_15_12) IP12_15_12 \ |
| 392 | FM(IP12_19_16) IP12_19_16 \ |
| 393 | FM(IP12_23_20) IP12_23_20 \ |
| 394 | FM(IP12_27_24) IP12_27_24 \ |
| 395 | FM(IP12_31_28) IP12_31_28 \ |
| 396 | |
Marek Vasut | 88e81ec | 2019-03-04 22:39:51 +0100 | [diff] [blame] | 397 | /* The bit numbering in MOD_SEL fields is reversed */ |
| 398 | #define REV4(f0, f1, f2, f3) f0 f2 f1 f3 |
| 399 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 400 | /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ |
| 401 | #define MOD_SEL0_30 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) |
| 402 | #define MOD_SEL0_29 FM(SEL_I2C3_0) FM(SEL_I2C3_1) |
| 403 | #define MOD_SEL0_28 FM(SEL_SCIF5_0) FM(SEL_SCIF5_1) |
| 404 | #define MOD_SEL0_27 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) |
| 405 | #define MOD_SEL0_26 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) |
| 406 | #define MOD_SEL0_25 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) |
Marek Vasut | 88e81ec | 2019-03-04 22:39:51 +0100 | [diff] [blame] | 407 | #define MOD_SEL0_24_23 REV4(FM(SEL_PWM0_0), FM(SEL_PWM0_1), FM(SEL_PWM0_2), F_(0, 0)) |
| 408 | #define MOD_SEL0_22_21 REV4(FM(SEL_PWM1_0), FM(SEL_PWM1_1), FM(SEL_PWM1_2), F_(0, 0)) |
| 409 | #define MOD_SEL0_20_19 REV4(FM(SEL_PWM2_0), FM(SEL_PWM2_1), FM(SEL_PWM2_2), F_(0, 0)) |
| 410 | #define MOD_SEL0_18_17 REV4(FM(SEL_PWM3_0), FM(SEL_PWM3_1), FM(SEL_PWM3_2), F_(0, 0)) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 411 | #define MOD_SEL0_15 FM(SEL_IRQ_0_0) FM(SEL_IRQ_0_1) |
| 412 | #define MOD_SEL0_14 FM(SEL_IRQ_1_0) FM(SEL_IRQ_1_1) |
| 413 | #define MOD_SEL0_13 FM(SEL_IRQ_2_0) FM(SEL_IRQ_2_1) |
| 414 | #define MOD_SEL0_12 FM(SEL_IRQ_3_0) FM(SEL_IRQ_3_1) |
| 415 | #define MOD_SEL0_11 FM(SEL_IRQ_4_0) FM(SEL_IRQ_4_1) |
| 416 | #define MOD_SEL0_10 FM(SEL_IRQ_5_0) FM(SEL_IRQ_5_1) |
| 417 | #define MOD_SEL0_5 FM(SEL_TMU_0_0) FM(SEL_TMU_0_1) |
| 418 | #define MOD_SEL0_4 FM(SEL_TMU_1_0) FM(SEL_TMU_1_1) |
| 419 | #define MOD_SEL0_3 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1) |
| 420 | #define MOD_SEL0_2 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1) |
| 421 | #define MOD_SEL0_1 FM(SEL_SCU_0) FM(SEL_SCU_1) |
| 422 | #define MOD_SEL0_0 FM(SEL_RFSO_0) FM(SEL_RFSO_1) |
| 423 | |
| 424 | #define MOD_SEL1_31 FM(SEL_CAN0_0) FM(SEL_CAN0_1) |
| 425 | #define MOD_SEL1_30 FM(SEL_CAN1_0) FM(SEL_CAN1_1) |
| 426 | #define MOD_SEL1_29 FM(SEL_I2C2_0) FM(SEL_I2C2_1) |
| 427 | #define MOD_SEL1_28 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1) |
| 428 | #define MOD_SEL1_27 FM(SEL_SCIF0_0) FM(SEL_SCIF0_1) |
| 429 | #define MOD_SEL1_26 FM(SEL_SSIF4_0) FM(SEL_SSIF4_1) |
| 430 | |
| 431 | |
| 432 | #define PINMUX_MOD_SELS \ |
| 433 | \ |
| 434 | MOD_SEL1_31 \ |
| 435 | MOD_SEL0_30 MOD_SEL1_30 \ |
| 436 | MOD_SEL0_29 MOD_SEL1_29 \ |
| 437 | MOD_SEL0_28 MOD_SEL1_28 \ |
| 438 | MOD_SEL0_27 MOD_SEL1_27 \ |
| 439 | MOD_SEL0_26 MOD_SEL1_26 \ |
| 440 | MOD_SEL0_25 \ |
| 441 | MOD_SEL0_24_23 \ |
| 442 | MOD_SEL0_22_21 \ |
| 443 | MOD_SEL0_20_19 \ |
| 444 | MOD_SEL0_18_17 \ |
| 445 | MOD_SEL0_15 \ |
| 446 | MOD_SEL0_14 \ |
| 447 | MOD_SEL0_13 \ |
| 448 | MOD_SEL0_12 \ |
| 449 | MOD_SEL0_11 \ |
| 450 | MOD_SEL0_10 \ |
| 451 | MOD_SEL0_5 \ |
| 452 | MOD_SEL0_4 \ |
| 453 | MOD_SEL0_3 \ |
| 454 | MOD_SEL0_2 \ |
| 455 | MOD_SEL0_1 \ |
| 456 | MOD_SEL0_0 |
| 457 | |
| 458 | enum { |
| 459 | PINMUX_RESERVED = 0, |
| 460 | |
| 461 | PINMUX_DATA_BEGIN, |
| 462 | GP_ALL(DATA), |
| 463 | PINMUX_DATA_END, |
| 464 | |
| 465 | #define F_(x, y) |
| 466 | #define FM(x) FN_##x, |
| 467 | PINMUX_FUNCTION_BEGIN, |
| 468 | GP_ALL(FN), |
| 469 | PINMUX_GPSR |
| 470 | PINMUX_IPSR |
| 471 | PINMUX_MOD_SELS |
| 472 | PINMUX_FUNCTION_END, |
| 473 | #undef F_ |
| 474 | #undef FM |
| 475 | |
| 476 | #define F_(x, y) |
| 477 | #define FM(x) x##_MARK, |
| 478 | PINMUX_MARK_BEGIN, |
| 479 | PINMUX_GPSR |
| 480 | PINMUX_IPSR |
| 481 | PINMUX_MOD_SELS |
| 482 | PINMUX_MARK_END, |
| 483 | #undef F_ |
| 484 | #undef FM |
| 485 | }; |
| 486 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 487 | static const u16 pinmux_data[] = { |
| 488 | PINMUX_DATA_GP_ALL(), |
| 489 | |
| 490 | PINMUX_SINGLE(USB0_OVC), |
| 491 | PINMUX_SINGLE(USB0_PWEN), |
| 492 | PINMUX_SINGLE(VI4_DATA4), |
| 493 | PINMUX_SINGLE(VI4_CLK), |
| 494 | PINMUX_SINGLE(TX2), |
| 495 | PINMUX_SINGLE(RX2), |
| 496 | PINMUX_SINGLE(AVB0_LINK), |
| 497 | PINMUX_SINGLE(AVB0_PHY_INT), |
| 498 | PINMUX_SINGLE(AVB0_MAGIC), |
| 499 | PINMUX_SINGLE(AVB0_MDC), |
| 500 | PINMUX_SINGLE(AVB0_MDIO), |
| 501 | PINMUX_SINGLE(AVB0_TXCREFCLK), |
| 502 | PINMUX_SINGLE(AVB0_TD3), |
| 503 | PINMUX_SINGLE(AVB0_TD2), |
| 504 | PINMUX_SINGLE(AVB0_TD1), |
| 505 | PINMUX_SINGLE(AVB0_TD0), |
| 506 | PINMUX_SINGLE(AVB0_TXC), |
| 507 | PINMUX_SINGLE(AVB0_TX_CTL), |
| 508 | PINMUX_SINGLE(AVB0_RD3), |
| 509 | PINMUX_SINGLE(AVB0_RD2), |
| 510 | PINMUX_SINGLE(AVB0_RD1), |
| 511 | PINMUX_SINGLE(AVB0_RD0), |
| 512 | PINMUX_SINGLE(AVB0_RXC), |
| 513 | PINMUX_SINGLE(AVB0_RX_CTL), |
| 514 | PINMUX_SINGLE(RPC_INT_N), |
| 515 | PINMUX_SINGLE(RPC_RESET_N), |
| 516 | PINMUX_SINGLE(QSPI1_SSL), |
| 517 | PINMUX_SINGLE(QSPI1_IO3), |
| 518 | PINMUX_SINGLE(QSPI1_IO2), |
| 519 | PINMUX_SINGLE(QSPI1_MISO_IO1), |
| 520 | PINMUX_SINGLE(QSPI1_MOSI_IO0), |
| 521 | PINMUX_SINGLE(QSPI1_SPCLK), |
| 522 | PINMUX_SINGLE(QSPI0_SSL), |
| 523 | PINMUX_SINGLE(QSPI0_IO3), |
| 524 | PINMUX_SINGLE(QSPI0_IO2), |
| 525 | PINMUX_SINGLE(QSPI0_MISO_IO1), |
| 526 | PINMUX_SINGLE(QSPI0_MOSI_IO0), |
| 527 | PINMUX_SINGLE(QSPI0_SPCLK), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 528 | PINMUX_SINGLE(SCL0), |
| 529 | PINMUX_SINGLE(SDA0), |
Marek Vasut | 88e81ec | 2019-03-04 22:39:51 +0100 | [diff] [blame] | 530 | PINMUX_SINGLE(MSIOF0_RXD), |
| 531 | PINMUX_SINGLE(MSIOF0_TXD), |
| 532 | PINMUX_SINGLE(MSIOF0_SYNC), |
| 533 | PINMUX_SINGLE(MSIOF0_SCK), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 534 | |
| 535 | /* IPSR0 */ |
| 536 | PINMUX_IPSR_MSEL(IP0_3_0, IRQ0_A, SEL_IRQ_0_0), |
| 537 | PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 538 | |
| 539 | PINMUX_IPSR_GPSR(IP0_7_4, MSIOF2_SCK), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 540 | |
| 541 | PINMUX_IPSR_GPSR(IP0_11_8, MSIOF2_TXD), |
| 542 | PINMUX_IPSR_MSEL(IP0_11_8, SCL3_A, SEL_I2C3_0), |
| 543 | |
| 544 | PINMUX_IPSR_GPSR(IP0_15_12, MSIOF2_RXD), |
| 545 | PINMUX_IPSR_MSEL(IP0_15_12, SDA3_A, SEL_I2C3_0), |
| 546 | |
| 547 | PINMUX_IPSR_GPSR(IP0_19_16, MLB_CLK), |
| 548 | PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_SYNC_A, SEL_MSIOF2_0), |
| 549 | PINMUX_IPSR_MSEL(IP0_19_16, SCK5_A, SEL_SCIF5_0), |
| 550 | |
| 551 | PINMUX_IPSR_GPSR(IP0_23_20, MLB_DAT), |
| 552 | PINMUX_IPSR_GPSR(IP0_23_20, MSIOF2_SS1), |
| 553 | PINMUX_IPSR_MSEL(IP0_23_20, RX5_A, SEL_SCIF5_0), |
| 554 | PINMUX_IPSR_MSEL(IP0_23_20, SCL3_B, SEL_I2C3_1), |
| 555 | |
| 556 | PINMUX_IPSR_GPSR(IP0_27_24, MLB_SIG), |
| 557 | PINMUX_IPSR_GPSR(IP0_27_24, MSIOF2_SS2), |
| 558 | PINMUX_IPSR_MSEL(IP0_27_24, TX5_A, SEL_SCIF5_0), |
| 559 | PINMUX_IPSR_MSEL(IP0_27_24, SDA3_B, SEL_I2C3_1), |
| 560 | |
| 561 | PINMUX_IPSR_GPSR(IP0_31_28, DU_DB0), |
| 562 | PINMUX_IPSR_GPSR(IP0_31_28, LCDOUT0), |
| 563 | PINMUX_IPSR_MSEL(IP0_31_28, MSIOF3_TXD_B, SEL_MSIOF3_1), |
| 564 | |
| 565 | /* IPSR1 */ |
| 566 | PINMUX_IPSR_GPSR(IP1_3_0, DU_DB1), |
| 567 | PINMUX_IPSR_GPSR(IP1_3_0, LCDOUT1), |
| 568 | PINMUX_IPSR_MSEL(IP1_3_0, MSIOF3_RXD_B, SEL_MSIOF3_1), |
| 569 | |
| 570 | PINMUX_IPSR_GPSR(IP1_7_4, DU_DB2), |
| 571 | PINMUX_IPSR_GPSR(IP1_7_4, LCDOUT2), |
| 572 | PINMUX_IPSR_MSEL(IP1_7_4, IRQ0_B, SEL_IRQ_0_1), |
| 573 | |
| 574 | PINMUX_IPSR_GPSR(IP1_11_8, DU_DB3), |
| 575 | PINMUX_IPSR_GPSR(IP1_11_8, LCDOUT3), |
| 576 | PINMUX_IPSR_MSEL(IP1_11_8, SCK5_B, SEL_SCIF5_1), |
| 577 | |
| 578 | PINMUX_IPSR_GPSR(IP1_15_12, DU_DB4), |
| 579 | PINMUX_IPSR_GPSR(IP1_15_12, LCDOUT4), |
| 580 | PINMUX_IPSR_MSEL(IP1_15_12, RX5_B, SEL_SCIF5_1), |
| 581 | |
| 582 | PINMUX_IPSR_GPSR(IP1_19_16, DU_DB5), |
| 583 | PINMUX_IPSR_GPSR(IP1_19_16, LCDOUT5), |
| 584 | PINMUX_IPSR_MSEL(IP1_19_16, TX5_B, SEL_SCIF5_1), |
| 585 | |
| 586 | PINMUX_IPSR_GPSR(IP1_23_20, DU_DB6), |
| 587 | PINMUX_IPSR_GPSR(IP1_23_20, LCDOUT6), |
| 588 | PINMUX_IPSR_MSEL(IP1_23_20, MSIOF3_SS1_B, SEL_MSIOF3_1), |
| 589 | |
| 590 | PINMUX_IPSR_GPSR(IP1_27_24, DU_DB7), |
| 591 | PINMUX_IPSR_GPSR(IP1_27_24, LCDOUT7), |
| 592 | PINMUX_IPSR_MSEL(IP1_27_24, MSIOF3_SS2_B, SEL_MSIOF3_1), |
| 593 | |
| 594 | PINMUX_IPSR_GPSR(IP1_31_28, DU_DG0), |
| 595 | PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT8), |
| 596 | PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SCK_B, SEL_MSIOF3_1), |
| 597 | |
| 598 | /* IPSR2 */ |
| 599 | PINMUX_IPSR_GPSR(IP2_3_0, DU_DG1), |
| 600 | PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT9), |
| 601 | PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_SYNC_B, SEL_MSIOF3_1), |
| 602 | |
| 603 | PINMUX_IPSR_GPSR(IP2_7_4, DU_DG2), |
| 604 | PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT10), |
| 605 | |
| 606 | PINMUX_IPSR_GPSR(IP2_11_8, DU_DG3), |
| 607 | PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT11), |
| 608 | PINMUX_IPSR_MSEL(IP2_11_8, IRQ1_A, SEL_IRQ_1_0), |
| 609 | |
| 610 | PINMUX_IPSR_GPSR(IP2_15_12, DU_DG4), |
| 611 | PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT12), |
| 612 | PINMUX_IPSR_MSEL(IP2_15_12, HSCK3_B, SEL_HSCIF3_1), |
| 613 | |
| 614 | PINMUX_IPSR_GPSR(IP2_19_16, DU_DG5), |
| 615 | PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT13), |
| 616 | PINMUX_IPSR_MSEL(IP2_19_16, HTX3_B, SEL_HSCIF3_1), |
| 617 | |
| 618 | PINMUX_IPSR_GPSR(IP2_23_20, DU_DG6), |
| 619 | PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT14), |
| 620 | PINMUX_IPSR_MSEL(IP2_23_20, HRX3_B, SEL_HSCIF3_1), |
| 621 | |
| 622 | PINMUX_IPSR_GPSR(IP2_27_24, DU_DG7), |
| 623 | PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT15), |
| 624 | PINMUX_IPSR_MSEL(IP2_27_24, SCK4_B, SEL_SCIF4_1), |
| 625 | |
| 626 | PINMUX_IPSR_GPSR(IP2_31_28, DU_DR0), |
| 627 | PINMUX_IPSR_GPSR(IP2_31_28, LCDOUT16), |
| 628 | PINMUX_IPSR_MSEL(IP2_31_28, RX4_B, SEL_SCIF4_1), |
| 629 | |
| 630 | /* IPSR3 */ |
| 631 | PINMUX_IPSR_GPSR(IP3_3_0, DU_DR1), |
| 632 | PINMUX_IPSR_GPSR(IP3_3_0, LCDOUT17), |
| 633 | PINMUX_IPSR_MSEL(IP3_3_0, TX4_B, SEL_SCIF4_1), |
| 634 | |
| 635 | PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2), |
| 636 | PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18), |
| 637 | PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2), |
| 638 | |
| 639 | PINMUX_IPSR_GPSR(IP3_11_8, DU_DR3), |
| 640 | PINMUX_IPSR_GPSR(IP3_11_8, LCDOUT19), |
| 641 | PINMUX_IPSR_MSEL(IP3_11_8, PWM1_B, SEL_PWM1_2), |
| 642 | |
| 643 | PINMUX_IPSR_GPSR(IP3_15_12, DU_DR4), |
| 644 | PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT20), |
| 645 | PINMUX_IPSR_MSEL(IP3_15_12, TCLK2_B, SEL_TMU_0_1), |
| 646 | |
| 647 | PINMUX_IPSR_GPSR(IP3_19_16, DU_DR5), |
| 648 | PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT21), |
| 649 | PINMUX_IPSR_GPSR(IP3_19_16, NMI), |
| 650 | |
| 651 | PINMUX_IPSR_GPSR(IP3_23_20, DU_DR6), |
| 652 | PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT22), |
| 653 | PINMUX_IPSR_MSEL(IP3_23_20, PWM2_B, SEL_PWM2_2), |
| 654 | |
| 655 | PINMUX_IPSR_GPSR(IP3_27_24, DU_DR7), |
| 656 | PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT23), |
| 657 | PINMUX_IPSR_MSEL(IP3_27_24, TCLK1_B, SEL_TMU_1_1), |
| 658 | |
| 659 | PINMUX_IPSR_GPSR(IP3_31_28, DU_DOTCLKOUT0), |
| 660 | PINMUX_IPSR_GPSR(IP3_31_28, QCLK), |
| 661 | |
| 662 | /* IPSR4 */ |
| 663 | PINMUX_IPSR_GPSR(IP4_3_0, DU_HSYNC), |
| 664 | PINMUX_IPSR_GPSR(IP4_3_0, QSTH_QHS), |
| 665 | PINMUX_IPSR_MSEL(IP4_3_0, IRQ3_A, SEL_IRQ_3_0), |
| 666 | |
| 667 | PINMUX_IPSR_GPSR(IP4_7_4, DU_VSYNC), |
| 668 | PINMUX_IPSR_GPSR(IP4_7_4, QSTVA_QVS), |
| 669 | PINMUX_IPSR_MSEL(IP4_7_4, IRQ4_A, SEL_IRQ_4_0), |
| 670 | |
| 671 | PINMUX_IPSR_GPSR(IP4_11_8, DU_DISP), |
| 672 | PINMUX_IPSR_GPSR(IP4_11_8, QSTVB_QVE), |
| 673 | PINMUX_IPSR_MSEL(IP4_11_8, PWM3_B, SEL_PWM3_2), |
| 674 | |
| 675 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DISP_CDE), |
| 676 | PINMUX_IPSR_GPSR(IP4_15_12, QCPV_QDE), |
| 677 | PINMUX_IPSR_MSEL(IP4_15_12, IRQ2_B, SEL_IRQ_2_1), |
| 678 | PINMUX_IPSR_GPSR(IP4_15_12, DU_DOTCLKIN1), |
| 679 | |
| 680 | PINMUX_IPSR_GPSR(IP4_19_16, DU_CDE), |
| 681 | PINMUX_IPSR_GPSR(IP4_19_16, QSTB_QHE), |
| 682 | PINMUX_IPSR_MSEL(IP4_19_16, SCK3_B, SEL_SCIF3_1), |
| 683 | |
| 684 | PINMUX_IPSR_GPSR(IP4_23_20, QPOLA), |
| 685 | PINMUX_IPSR_MSEL(IP4_23_20, RX3_B, SEL_SCIF3_1), |
| 686 | |
| 687 | PINMUX_IPSR_GPSR(IP4_27_24, QPOLB), |
| 688 | PINMUX_IPSR_MSEL(IP4_27_24, TX3_B, SEL_SCIF3_1), |
| 689 | |
| 690 | PINMUX_IPSR_GPSR(IP4_31_28, VI4_DATA0), |
| 691 | PINMUX_IPSR_MSEL(IP4_31_28, PWM0_A, SEL_PWM0_0), |
| 692 | |
| 693 | /* IPSR5 */ |
| 694 | PINMUX_IPSR_GPSR(IP5_3_0, VI4_DATA1), |
| 695 | PINMUX_IPSR_MSEL(IP5_3_0, PWM1_A, SEL_PWM1_0), |
| 696 | |
| 697 | PINMUX_IPSR_GPSR(IP5_7_4, VI4_DATA2), |
| 698 | PINMUX_IPSR_MSEL(IP5_7_4, PWM2_A, SEL_PWM2_0), |
| 699 | |
| 700 | PINMUX_IPSR_GPSR(IP5_11_8, VI4_DATA3), |
| 701 | PINMUX_IPSR_MSEL(IP5_11_8, PWM3_A, SEL_PWM3_0), |
| 702 | |
| 703 | PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA5), |
| 704 | PINMUX_IPSR_MSEL(IP5_15_12, SCK4_A, SEL_SCIF4_0), |
| 705 | |
| 706 | PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA6), |
| 707 | PINMUX_IPSR_MSEL(IP5_19_16, IRQ2_A, SEL_IRQ_2_0), |
| 708 | |
| 709 | PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA7), |
| 710 | PINMUX_IPSR_MSEL(IP5_23_20, TCLK2_A, SEL_TMU_0_0), |
| 711 | |
| 712 | PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA8), |
| 713 | |
| 714 | PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA9), |
| 715 | PINMUX_IPSR_MSEL(IP5_31_28, MSIOF3_SS2_A, SEL_MSIOF3_0), |
| 716 | PINMUX_IPSR_MSEL(IP5_31_28, IRQ1_B, SEL_IRQ_1_1), |
| 717 | |
| 718 | /* IPSR6 */ |
| 719 | PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA10), |
| 720 | PINMUX_IPSR_MSEL(IP6_3_0, RX4_A, SEL_SCIF4_0), |
| 721 | |
| 722 | PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA11), |
| 723 | PINMUX_IPSR_MSEL(IP6_7_4, TX4_A, SEL_SCIF4_0), |
| 724 | |
| 725 | PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA12), |
| 726 | PINMUX_IPSR_MSEL(IP6_11_8, TCLK1_A, SEL_TMU_1_0), |
| 727 | |
| 728 | PINMUX_IPSR_GPSR(IP6_15_12, VI4_DATA13), |
| 729 | PINMUX_IPSR_MSEL(IP6_15_12, MSIOF3_SS1_A, SEL_MSIOF3_0), |
| 730 | PINMUX_IPSR_GPSR(IP6_15_12, HCTS3_N), |
| 731 | |
| 732 | PINMUX_IPSR_GPSR(IP6_19_16, VI4_DATA14), |
| 733 | PINMUX_IPSR_MSEL(IP6_19_16, SSI_SCK4_B, SEL_SSIF4_1), |
| 734 | PINMUX_IPSR_GPSR(IP6_19_16, HRTS3_N), |
| 735 | |
| 736 | PINMUX_IPSR_GPSR(IP6_23_20, VI4_DATA15), |
| 737 | PINMUX_IPSR_MSEL(IP6_23_20, SSI_SDATA4_B, SEL_SSIF4_1), |
| 738 | |
| 739 | PINMUX_IPSR_GPSR(IP6_27_24, VI4_DATA16), |
| 740 | PINMUX_IPSR_MSEL(IP6_27_24, HRX3_A, SEL_HSCIF3_0), |
| 741 | |
| 742 | PINMUX_IPSR_GPSR(IP6_31_28, VI4_DATA17), |
| 743 | PINMUX_IPSR_MSEL(IP6_31_28, HTX3_A, SEL_HSCIF3_0), |
| 744 | |
| 745 | /* IPSR7 */ |
| 746 | PINMUX_IPSR_GPSR(IP7_3_0, VI4_DATA18), |
| 747 | PINMUX_IPSR_MSEL(IP7_3_0, HSCK3_A, SEL_HSCIF3_0), |
| 748 | |
| 749 | PINMUX_IPSR_GPSR(IP7_7_4, VI4_DATA19), |
| 750 | PINMUX_IPSR_MSEL(IP7_7_4, SSI_WS4_B, SEL_SSIF4_1), |
| 751 | PINMUX_IPSR_GPSR(IP7_7_4, NFDATA15), |
| 752 | |
| 753 | PINMUX_IPSR_GPSR(IP7_11_8, VI4_DATA20), |
| 754 | PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SYNC_A, SEL_MSIOF3_0), |
| 755 | PINMUX_IPSR_GPSR(IP7_11_8, NFDATA14), |
| 756 | |
| 757 | PINMUX_IPSR_GPSR(IP7_15_12, VI4_DATA21), |
| 758 | PINMUX_IPSR_MSEL(IP7_15_12, MSIOF3_TXD_A, SEL_MSIOF3_0), |
| 759 | |
| 760 | PINMUX_IPSR_GPSR(IP7_15_12, NFDATA13), |
| 761 | PINMUX_IPSR_GPSR(IP7_19_16, VI4_DATA22), |
| 762 | PINMUX_IPSR_MSEL(IP7_19_16, MSIOF3_RXD_A, SEL_MSIOF3_0), |
| 763 | |
| 764 | PINMUX_IPSR_GPSR(IP7_19_16, NFDATA12), |
| 765 | PINMUX_IPSR_GPSR(IP7_23_20, VI4_DATA23), |
| 766 | PINMUX_IPSR_MSEL(IP7_23_20, MSIOF3_SCK_A, SEL_MSIOF3_0), |
| 767 | |
| 768 | PINMUX_IPSR_GPSR(IP7_23_20, NFDATA11), |
| 769 | |
| 770 | PINMUX_IPSR_GPSR(IP7_27_24, VI4_VSYNC_N), |
| 771 | PINMUX_IPSR_MSEL(IP7_27_24, SCK1_B, SEL_SCIF1_1), |
| 772 | PINMUX_IPSR_GPSR(IP7_27_24, NFDATA10), |
| 773 | |
| 774 | PINMUX_IPSR_GPSR(IP7_31_28, VI4_HSYNC_N), |
| 775 | PINMUX_IPSR_MSEL(IP7_31_28, RX1_B, SEL_SCIF1_1), |
| 776 | PINMUX_IPSR_GPSR(IP7_31_28, NFDATA9), |
| 777 | |
| 778 | /* IPSR8 */ |
| 779 | PINMUX_IPSR_GPSR(IP8_3_0, VI4_FIELD), |
| 780 | PINMUX_IPSR_GPSR(IP8_3_0, AUDIO_CLKB), |
| 781 | PINMUX_IPSR_MSEL(IP8_3_0, IRQ5_A, SEL_IRQ_5_0), |
| 782 | PINMUX_IPSR_GPSR(IP8_3_0, SCIF_CLK), |
| 783 | PINMUX_IPSR_GPSR(IP8_3_0, NFDATA8), |
| 784 | |
| 785 | PINMUX_IPSR_GPSR(IP8_7_4, VI4_CLKENB), |
| 786 | PINMUX_IPSR_MSEL(IP8_7_4, TX1_B, SEL_SCIF1_1), |
| 787 | PINMUX_IPSR_GPSR(IP8_7_4, NFWP_N), |
| 788 | PINMUX_IPSR_MSEL(IP8_7_4, DVC_MUTE_A, SEL_SCU_0), |
| 789 | |
| 790 | PINMUX_IPSR_GPSR(IP8_11_8, NFALE), |
| 791 | PINMUX_IPSR_MSEL(IP8_11_8, SCL2_B, SEL_I2C2_1), |
| 792 | PINMUX_IPSR_MSEL(IP8_11_8, IRQ3_B, SEL_IRQ_3_1), |
| 793 | PINMUX_IPSR_MSEL(IP8_11_8, PWM0_C, SEL_PWM0_1), |
| 794 | |
| 795 | PINMUX_IPSR_GPSR(IP8_15_12, NFCLE), |
| 796 | PINMUX_IPSR_MSEL(IP8_15_12, SDA2_B, SEL_I2C2_1), |
| 797 | PINMUX_IPSR_MSEL(IP8_15_12, SCK3_A, SEL_SCIF3_0), |
| 798 | PINMUX_IPSR_MSEL(IP8_15_12, PWM1_C, SEL_PWM1_1), |
| 799 | |
| 800 | PINMUX_IPSR_GPSR(IP8_19_16, NFCE_N), |
| 801 | PINMUX_IPSR_MSEL(IP8_19_16, RX3_A, SEL_SCIF3_0), |
| 802 | PINMUX_IPSR_MSEL(IP8_19_16, PWM2_C, SEL_PWM2_1), |
| 803 | |
| 804 | PINMUX_IPSR_GPSR(IP8_23_20, NFRB_N), |
| 805 | PINMUX_IPSR_MSEL(IP8_23_20, TX3_A, SEL_SCIF3_0), |
| 806 | PINMUX_IPSR_MSEL(IP8_23_20, PWM3_C, SEL_PWM3_1), |
| 807 | |
| 808 | PINMUX_IPSR_GPSR(IP8_27_24, NFRE_N), |
| 809 | PINMUX_IPSR_GPSR(IP8_27_24, MMC_CMD), |
| 810 | |
| 811 | PINMUX_IPSR_GPSR(IP8_31_28, NFWE_N), |
| 812 | PINMUX_IPSR_GPSR(IP8_31_28, MMC_CLK), |
| 813 | |
| 814 | /* IPSR9 */ |
| 815 | PINMUX_IPSR_GPSR(IP9_3_0, NFDATA0), |
| 816 | PINMUX_IPSR_GPSR(IP9_3_0, MMC_D0), |
| 817 | |
| 818 | PINMUX_IPSR_GPSR(IP9_7_4, NFDATA1), |
| 819 | PINMUX_IPSR_GPSR(IP9_7_4, MMC_D1), |
| 820 | |
| 821 | PINMUX_IPSR_GPSR(IP9_11_8, NFDATA2), |
| 822 | PINMUX_IPSR_GPSR(IP9_11_8, MMC_D2), |
| 823 | |
| 824 | PINMUX_IPSR_GPSR(IP9_15_12, NFDATA3), |
| 825 | PINMUX_IPSR_GPSR(IP9_15_12, MMC_D3), |
| 826 | |
| 827 | PINMUX_IPSR_GPSR(IP9_19_16, NFDATA4), |
| 828 | PINMUX_IPSR_GPSR(IP9_19_16, MMC_D4), |
| 829 | |
| 830 | PINMUX_IPSR_GPSR(IP9_23_20, NFDATA5), |
| 831 | PINMUX_IPSR_GPSR(IP9_23_20, MMC_D5), |
| 832 | |
| 833 | PINMUX_IPSR_GPSR(IP9_27_24, NFDATA6), |
| 834 | PINMUX_IPSR_GPSR(IP9_27_24, MMC_D6), |
| 835 | |
| 836 | PINMUX_IPSR_GPSR(IP9_31_28, NFDATA7), |
| 837 | PINMUX_IPSR_GPSR(IP9_31_28, MMC_D7), |
| 838 | |
| 839 | /* IPSR10 */ |
| 840 | PINMUX_IPSR_GPSR(IP10_3_0, AUDIO_CLKA), |
| 841 | PINMUX_IPSR_MSEL(IP10_3_0, DVC_MUTE_B, SEL_SCU_1), |
| 842 | |
| 843 | PINMUX_IPSR_GPSR(IP10_7_4, SSI_SCK34), |
| 844 | PINMUX_IPSR_MSEL(IP10_7_4, FSO_CFE_0_N_A, SEL_RFSO_0), |
| 845 | |
| 846 | PINMUX_IPSR_GPSR(IP10_11_8, SSI_SDATA3), |
| 847 | PINMUX_IPSR_MSEL(IP10_11_8, FSO_CFE_1_N_A, SEL_RFSO_0), |
| 848 | |
| 849 | PINMUX_IPSR_GPSR(IP10_15_12, SSI_WS34), |
| 850 | PINMUX_IPSR_MSEL(IP10_15_12, FSO_TOE_N_A, SEL_RFSO_0), |
| 851 | |
| 852 | PINMUX_IPSR_MSEL(IP10_19_16, SSI_SCK4_A, SEL_SSIF4_0), |
| 853 | PINMUX_IPSR_GPSR(IP10_19_16, HSCK0), |
| 854 | PINMUX_IPSR_GPSR(IP10_19_16, AUDIO_CLKOUT), |
| 855 | PINMUX_IPSR_MSEL(IP10_19_16, CAN0_RX_B, SEL_CAN0_1), |
| 856 | PINMUX_IPSR_MSEL(IP10_19_16, IRQ4_B, SEL_IRQ_4_1), |
| 857 | |
| 858 | PINMUX_IPSR_MSEL(IP10_23_20, SSI_SDATA4_A, SEL_SSIF4_0), |
| 859 | PINMUX_IPSR_GPSR(IP10_23_20, HTX0), |
| 860 | PINMUX_IPSR_MSEL(IP10_23_20, SCL2_A, SEL_I2C2_0), |
| 861 | PINMUX_IPSR_MSEL(IP10_23_20, CAN1_RX_B, SEL_CAN1_1), |
| 862 | |
| 863 | PINMUX_IPSR_MSEL(IP10_27_24, SSI_WS4_A, SEL_SSIF4_0), |
| 864 | PINMUX_IPSR_GPSR(IP10_27_24, HRX0), |
| 865 | PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0), |
| 866 | PINMUX_IPSR_MSEL(IP10_27_24, CAN1_TX_B, SEL_CAN1_1), |
| 867 | |
| 868 | PINMUX_IPSR_GPSR(IP10_31_28, SCL1), |
| 869 | PINMUX_IPSR_GPSR(IP10_31_28, CTS1_N), |
| 870 | |
| 871 | /* IPSR11 */ |
| 872 | PINMUX_IPSR_GPSR(IP11_3_0, SDA1), |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 873 | PINMUX_IPSR_GPSR(IP11_3_0, RTS1_N), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 874 | |
| 875 | PINMUX_IPSR_GPSR(IP11_7_4, MSIOF1_SCK), |
| 876 | PINMUX_IPSR_MSEL(IP11_7_4, AVB0_AVTP_PPS_B, SEL_ETHERAVB_1), |
| 877 | |
| 878 | PINMUX_IPSR_GPSR(IP11_11_8, MSIOF1_TXD), |
| 879 | PINMUX_IPSR_MSEL(IP11_11_8, AVB0_AVTP_CAPTURE_B, SEL_ETHERAVB_1), |
| 880 | |
| 881 | PINMUX_IPSR_GPSR(IP11_15_12, MSIOF1_RXD), |
| 882 | PINMUX_IPSR_MSEL(IP11_15_12, AVB0_AVTP_MATCH_B, SEL_ETHERAVB_1), |
| 883 | |
| 884 | PINMUX_IPSR_MSEL(IP11_19_16, SCK0_A, SEL_SCIF0_0), |
| 885 | PINMUX_IPSR_GPSR(IP11_19_16, MSIOF1_SYNC), |
| 886 | PINMUX_IPSR_MSEL(IP11_19_16, FSO_CFE_0_N_B, SEL_RFSO_1), |
| 887 | |
| 888 | PINMUX_IPSR_MSEL(IP11_23_20, RX0_A, SEL_SCIF0_0), |
| 889 | PINMUX_IPSR_GPSR(IP11_23_20, MSIOF0_SS1), |
| 890 | PINMUX_IPSR_MSEL(IP11_23_20, FSO_CFE_1_N_B, SEL_RFSO_1), |
| 891 | |
| 892 | PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0), |
| 893 | PINMUX_IPSR_GPSR(IP11_27_24, MSIOF0_SS2), |
| 894 | PINMUX_IPSR_MSEL(IP11_27_24, FSO_TOE_N_B, SEL_RFSO_1), |
| 895 | |
| 896 | PINMUX_IPSR_MSEL(IP11_31_28, SCK1_A, SEL_SCIF1_0), |
| 897 | PINMUX_IPSR_GPSR(IP11_31_28, MSIOF1_SS2), |
| 898 | PINMUX_IPSR_GPSR(IP11_31_28, TPU0TO2_B), |
| 899 | PINMUX_IPSR_MSEL(IP11_31_28, CAN0_TX_B, SEL_CAN0_1), |
| 900 | PINMUX_IPSR_GPSR(IP11_31_28, AUDIO_CLKOUT1), |
| 901 | |
| 902 | /* IPSR12 */ |
| 903 | PINMUX_IPSR_MSEL(IP12_3_0, RX1_A, SEL_SCIF1_0), |
| 904 | PINMUX_IPSR_GPSR(IP12_3_0, CTS0_N), |
| 905 | PINMUX_IPSR_GPSR(IP12_3_0, TPU0TO0_B), |
| 906 | |
| 907 | PINMUX_IPSR_MSEL(IP12_7_4, TX1_A, SEL_SCIF1_0), |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 908 | PINMUX_IPSR_GPSR(IP12_7_4, RTS0_N), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 909 | PINMUX_IPSR_GPSR(IP12_7_4, TPU0TO1_B), |
| 910 | |
| 911 | PINMUX_IPSR_GPSR(IP12_11_8, SCK2), |
| 912 | PINMUX_IPSR_GPSR(IP12_11_8, MSIOF1_SS1), |
| 913 | PINMUX_IPSR_GPSR(IP12_11_8, TPU0TO3_B), |
| 914 | |
| 915 | PINMUX_IPSR_GPSR(IP12_15_12, TPU0TO0_A), |
| 916 | PINMUX_IPSR_MSEL(IP12_15_12, AVB0_AVTP_CAPTURE_A, SEL_ETHERAVB_0), |
| 917 | PINMUX_IPSR_GPSR(IP12_15_12, HCTS0_N), |
| 918 | |
| 919 | PINMUX_IPSR_GPSR(IP12_19_16, TPU0TO1_A), |
| 920 | PINMUX_IPSR_MSEL(IP12_19_16, AVB0_AVTP_MATCH_A, SEL_ETHERAVB_0), |
| 921 | PINMUX_IPSR_GPSR(IP12_19_16, HRTS0_N), |
| 922 | |
| 923 | PINMUX_IPSR_GPSR(IP12_23_20, CAN_CLK), |
| 924 | PINMUX_IPSR_MSEL(IP12_23_20, AVB0_AVTP_PPS_A, SEL_ETHERAVB_0), |
| 925 | PINMUX_IPSR_MSEL(IP12_23_20, SCK0_B, SEL_SCIF0_1), |
| 926 | PINMUX_IPSR_MSEL(IP12_23_20, IRQ5_B, SEL_IRQ_5_1), |
| 927 | |
| 928 | PINMUX_IPSR_MSEL(IP12_27_24, CAN0_RX_A, SEL_CAN0_0), |
| 929 | PINMUX_IPSR_GPSR(IP12_27_24, CANFD0_RX), |
| 930 | PINMUX_IPSR_MSEL(IP12_27_24, RX0_B, SEL_SCIF0_1), |
| 931 | |
| 932 | PINMUX_IPSR_MSEL(IP12_31_28, CAN0_TX_A, SEL_CAN0_0), |
| 933 | PINMUX_IPSR_GPSR(IP12_31_28, CANFD0_TX), |
| 934 | PINMUX_IPSR_MSEL(IP12_31_28, TX0_B, SEL_SCIF0_1), |
| 935 | |
| 936 | /* IPSR13 */ |
| 937 | PINMUX_IPSR_MSEL(IP13_3_0, CAN1_RX_A, SEL_CAN1_0), |
| 938 | PINMUX_IPSR_GPSR(IP13_3_0, CANFD1_RX), |
| 939 | PINMUX_IPSR_GPSR(IP13_3_0, TPU0TO2_A), |
| 940 | |
| 941 | PINMUX_IPSR_MSEL(IP13_7_4, CAN1_TX_A, SEL_CAN1_0), |
| 942 | PINMUX_IPSR_GPSR(IP13_7_4, CANFD1_TX), |
| 943 | PINMUX_IPSR_GPSR(IP13_7_4, TPU0TO3_A), |
| 944 | }; |
| 945 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 946 | /* |
| 947 | * Pins not associated with a GPIO port. |
| 948 | */ |
| 949 | enum { |
| 950 | GP_ASSIGN_LAST(), |
| 951 | NOGP_ALL(), |
| 952 | }; |
| 953 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 954 | static const struct sh_pfc_pin pinmux_pins[] = { |
| 955 | PINMUX_GPIO_GP_ALL(), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 956 | PINMUX_NOGP_ALL(), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 957 | }; |
| 958 | |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 959 | /* - AUDIO CLOCK ------------------------------------------------------------- */ |
| 960 | static const unsigned int audio_clk_a_pins[] = { |
| 961 | /* CLK A */ |
| 962 | RCAR_GP_PIN(4, 1), |
| 963 | }; |
| 964 | static const unsigned int audio_clk_a_mux[] = { |
| 965 | AUDIO_CLKA_MARK, |
| 966 | }; |
| 967 | static const unsigned int audio_clk_b_pins[] = { |
| 968 | /* CLK B */ |
| 969 | RCAR_GP_PIN(2, 27), |
| 970 | }; |
| 971 | static const unsigned int audio_clk_b_mux[] = { |
| 972 | AUDIO_CLKB_MARK, |
| 973 | }; |
| 974 | static const unsigned int audio_clkout_pins[] = { |
| 975 | /* CLKOUT */ |
| 976 | RCAR_GP_PIN(4, 5), |
| 977 | }; |
| 978 | static const unsigned int audio_clkout_mux[] = { |
| 979 | AUDIO_CLKOUT_MARK, |
| 980 | }; |
| 981 | static const unsigned int audio_clkout1_pins[] = { |
| 982 | /* CLKOUT1 */ |
| 983 | RCAR_GP_PIN(4, 22), |
| 984 | }; |
| 985 | static const unsigned int audio_clkout1_mux[] = { |
| 986 | AUDIO_CLKOUT1_MARK, |
| 987 | }; |
| 988 | |
| 989 | /* - EtherAVB --------------------------------------------------------------- */ |
| 990 | static const unsigned int avb0_link_pins[] = { |
| 991 | /* AVB0_LINK */ |
| 992 | RCAR_GP_PIN(5, 20), |
| 993 | }; |
| 994 | static const unsigned int avb0_link_mux[] = { |
| 995 | AVB0_LINK_MARK, |
| 996 | }; |
| 997 | static const unsigned int avb0_magic_pins[] = { |
| 998 | /* AVB0_MAGIC */ |
| 999 | RCAR_GP_PIN(5, 18), |
| 1000 | }; |
| 1001 | static const unsigned int avb0_magic_mux[] = { |
| 1002 | AVB0_MAGIC_MARK, |
| 1003 | }; |
| 1004 | static const unsigned int avb0_phy_int_pins[] = { |
| 1005 | /* AVB0_PHY_INT */ |
| 1006 | RCAR_GP_PIN(5, 19), |
| 1007 | }; |
| 1008 | static const unsigned int avb0_phy_int_mux[] = { |
| 1009 | AVB0_PHY_INT_MARK, |
| 1010 | }; |
| 1011 | static const unsigned int avb0_mdio_pins[] = { |
| 1012 | /* AVB0_MDC, AVB0_MDIO */ |
| 1013 | RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 16), |
| 1014 | }; |
| 1015 | static const unsigned int avb0_mdio_mux[] = { |
| 1016 | AVB0_MDC_MARK, AVB0_MDIO_MARK, |
| 1017 | }; |
| 1018 | static const unsigned int avb0_mii_pins[] = { |
| 1019 | /* |
| 1020 | * AVB0_TX_CTL, AVB0_TXC, AVB0_TD0, |
| 1021 | * AVB0_TD1, AVB0_TD2, AVB0_TD3, |
| 1022 | * AVB0_RX_CTL, AVB0_RXC, AVB0_RD0, |
| 1023 | * AVB0_RD1, AVB0_RD2, AVB0_RD3, |
| 1024 | * AVB0_TXCREFCLK |
| 1025 | */ |
| 1026 | RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11), |
| 1027 | RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), |
| 1028 | RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5), |
| 1029 | RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8), |
| 1030 | RCAR_GP_PIN(5, 15), |
| 1031 | }; |
| 1032 | static const unsigned int avb0_mii_mux[] = { |
| 1033 | AVB0_TX_CTL_MARK, AVB0_TXC_MARK, AVB0_TD0_MARK, |
| 1034 | AVB0_TD1_MARK, AVB0_TD2_MARK, AVB0_TD3_MARK, |
| 1035 | AVB0_RX_CTL_MARK, AVB0_RXC_MARK, AVB0_RD0_MARK, |
| 1036 | AVB0_RD1_MARK, AVB0_RD2_MARK, AVB0_RD3_MARK, |
| 1037 | AVB0_TXCREFCLK_MARK, |
| 1038 | }; |
| 1039 | static const unsigned int avb0_avtp_pps_a_pins[] = { |
| 1040 | /* AVB0_AVTP_PPS_A */ |
| 1041 | RCAR_GP_PIN(5, 2), |
| 1042 | }; |
| 1043 | static const unsigned int avb0_avtp_pps_a_mux[] = { |
| 1044 | AVB0_AVTP_PPS_A_MARK, |
| 1045 | }; |
| 1046 | static const unsigned int avb0_avtp_match_a_pins[] = { |
| 1047 | /* AVB0_AVTP_MATCH_A */ |
| 1048 | RCAR_GP_PIN(5, 1), |
| 1049 | }; |
| 1050 | static const unsigned int avb0_avtp_match_a_mux[] = { |
| 1051 | AVB0_AVTP_MATCH_A_MARK, |
| 1052 | }; |
| 1053 | static const unsigned int avb0_avtp_capture_a_pins[] = { |
| 1054 | /* AVB0_AVTP_CAPTURE_A */ |
| 1055 | RCAR_GP_PIN(5, 0), |
| 1056 | }; |
| 1057 | static const unsigned int avb0_avtp_capture_a_mux[] = { |
| 1058 | AVB0_AVTP_CAPTURE_A_MARK, |
| 1059 | }; |
| 1060 | static const unsigned int avb0_avtp_pps_b_pins[] = { |
| 1061 | /* AVB0_AVTP_PPS_B */ |
| 1062 | RCAR_GP_PIN(4, 16), |
| 1063 | }; |
| 1064 | static const unsigned int avb0_avtp_pps_b_mux[] = { |
| 1065 | AVB0_AVTP_PPS_B_MARK, |
| 1066 | }; |
| 1067 | static const unsigned int avb0_avtp_match_b_pins[] = { |
| 1068 | /* AVB0_AVTP_MATCH_B */ |
| 1069 | RCAR_GP_PIN(4, 18), |
| 1070 | }; |
| 1071 | static const unsigned int avb0_avtp_match_b_mux[] = { |
| 1072 | AVB0_AVTP_MATCH_B_MARK, |
| 1073 | }; |
| 1074 | static const unsigned int avb0_avtp_capture_b_pins[] = { |
| 1075 | /* AVB0_AVTP_CAPTURE_B */ |
| 1076 | RCAR_GP_PIN(4, 17), |
| 1077 | }; |
| 1078 | static const unsigned int avb0_avtp_capture_b_mux[] = { |
| 1079 | AVB0_AVTP_CAPTURE_B_MARK, |
| 1080 | }; |
| 1081 | |
| 1082 | /* - CAN ------------------------------------------------------------------ */ |
| 1083 | static const unsigned int can0_data_a_pins[] = { |
| 1084 | /* TX, RX */ |
| 1085 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), |
| 1086 | }; |
| 1087 | static const unsigned int can0_data_a_mux[] = { |
| 1088 | CAN0_TX_A_MARK, CAN0_RX_A_MARK, |
| 1089 | }; |
| 1090 | static const unsigned int can0_data_b_pins[] = { |
| 1091 | /* TX, RX */ |
| 1092 | RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 5), |
| 1093 | }; |
| 1094 | static const unsigned int can0_data_b_mux[] = { |
| 1095 | CAN0_TX_B_MARK, CAN0_RX_B_MARK, |
| 1096 | }; |
| 1097 | static const unsigned int can1_data_a_pins[] = { |
| 1098 | /* TX, RX */ |
| 1099 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), |
| 1100 | }; |
| 1101 | static const unsigned int can1_data_a_mux[] = { |
| 1102 | CAN1_TX_A_MARK, CAN1_RX_A_MARK, |
| 1103 | }; |
| 1104 | static const unsigned int can1_data_b_pins[] = { |
| 1105 | /* TX, RX */ |
| 1106 | RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 6), |
| 1107 | }; |
| 1108 | static const unsigned int can1_data_b_mux[] = { |
| 1109 | CAN1_TX_B_MARK, CAN1_RX_B_MARK, |
| 1110 | }; |
| 1111 | |
| 1112 | /* - CAN Clock -------------------------------------------------------------- */ |
| 1113 | static const unsigned int can_clk_pins[] = { |
| 1114 | /* CLK */ |
| 1115 | RCAR_GP_PIN(5, 2), |
| 1116 | }; |
| 1117 | static const unsigned int can_clk_mux[] = { |
| 1118 | CAN_CLK_MARK, |
| 1119 | }; |
| 1120 | |
| 1121 | /* - CAN FD ----------------------------------------------------------------- */ |
| 1122 | static const unsigned int canfd0_data_pins[] = { |
| 1123 | /* TX, RX */ |
| 1124 | RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 31), |
| 1125 | }; |
| 1126 | static const unsigned int canfd0_data_mux[] = { |
| 1127 | CANFD0_TX_MARK, CANFD0_RX_MARK, |
| 1128 | }; |
| 1129 | static const unsigned int canfd1_data_pins[] = { |
| 1130 | /* TX, RX */ |
| 1131 | RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 29), |
| 1132 | }; |
| 1133 | static const unsigned int canfd1_data_mux[] = { |
| 1134 | CANFD1_TX_MARK, CANFD1_RX_MARK, |
| 1135 | }; |
| 1136 | |
| 1137 | /* - DU --------------------------------------------------------------------- */ |
| 1138 | static const unsigned int du_rgb666_pins[] = { |
| 1139 | /* R[7:2], G[7:2], B[7:2] */ |
| 1140 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), |
| 1141 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), |
| 1142 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), |
| 1143 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), |
| 1144 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), |
| 1145 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), |
| 1146 | }; |
| 1147 | static const unsigned int du_rgb666_mux[] = { |
| 1148 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, |
| 1149 | DU_DR3_MARK, DU_DR2_MARK, |
| 1150 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, |
| 1151 | DU_DG3_MARK, DU_DG2_MARK, |
| 1152 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, |
| 1153 | DU_DB3_MARK, DU_DB2_MARK, |
| 1154 | }; |
| 1155 | static const unsigned int du_rgb888_pins[] = { |
| 1156 | /* R[7:0], G[7:0], B[7:0] */ |
| 1157 | RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), |
| 1158 | RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), |
| 1159 | RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), |
| 1160 | RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), |
| 1161 | RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10), |
| 1162 | RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8), |
| 1163 | RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), |
| 1164 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), |
| 1165 | RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), |
| 1166 | }; |
| 1167 | static const unsigned int du_rgb888_mux[] = { |
| 1168 | DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, |
| 1169 | DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, |
| 1170 | DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, |
| 1171 | DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, |
| 1172 | DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, |
| 1173 | DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, |
| 1174 | }; |
| 1175 | static const unsigned int du_clk_in_1_pins[] = { |
| 1176 | /* CLKIN */ |
| 1177 | RCAR_GP_PIN(1, 28), |
| 1178 | }; |
| 1179 | static const unsigned int du_clk_in_1_mux[] = { |
| 1180 | DU_DOTCLKIN1_MARK |
| 1181 | }; |
| 1182 | static const unsigned int du_clk_out_0_pins[] = { |
| 1183 | /* CLKOUT */ |
| 1184 | RCAR_GP_PIN(1, 24), |
| 1185 | }; |
| 1186 | static const unsigned int du_clk_out_0_mux[] = { |
| 1187 | DU_DOTCLKOUT0_MARK |
| 1188 | }; |
| 1189 | static const unsigned int du_sync_pins[] = { |
| 1190 | /* VSYNC, HSYNC */ |
| 1191 | RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25), |
| 1192 | }; |
| 1193 | static const unsigned int du_sync_mux[] = { |
| 1194 | DU_VSYNC_MARK, DU_HSYNC_MARK |
| 1195 | }; |
| 1196 | static const unsigned int du_disp_cde_pins[] = { |
| 1197 | /* DISP_CDE */ |
| 1198 | RCAR_GP_PIN(1, 28), |
| 1199 | }; |
| 1200 | static const unsigned int du_disp_cde_mux[] = { |
| 1201 | DU_DISP_CDE_MARK, |
| 1202 | }; |
| 1203 | static const unsigned int du_cde_pins[] = { |
| 1204 | /* CDE */ |
| 1205 | RCAR_GP_PIN(1, 29), |
| 1206 | }; |
| 1207 | static const unsigned int du_cde_mux[] = { |
| 1208 | DU_CDE_MARK, |
| 1209 | }; |
| 1210 | static const unsigned int du_disp_pins[] = { |
| 1211 | /* DISP */ |
| 1212 | RCAR_GP_PIN(1, 27), |
| 1213 | }; |
| 1214 | static const unsigned int du_disp_mux[] = { |
| 1215 | DU_DISP_MARK, |
| 1216 | }; |
| 1217 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1218 | /* - I2C -------------------------------------------------------------------- */ |
| 1219 | static const unsigned int i2c0_pins[] = { |
| 1220 | /* SCL, SDA */ |
| 1221 | RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9), |
| 1222 | }; |
| 1223 | static const unsigned int i2c0_mux[] = { |
| 1224 | SCL0_MARK, SDA0_MARK, |
| 1225 | }; |
| 1226 | static const unsigned int i2c1_pins[] = { |
| 1227 | /* SCL, SDA */ |
| 1228 | RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), |
| 1229 | }; |
| 1230 | static const unsigned int i2c1_mux[] = { |
| 1231 | SCL1_MARK, SDA1_MARK, |
| 1232 | }; |
| 1233 | static const unsigned int i2c2_a_pins[] = { |
| 1234 | /* SCL, SDA */ |
| 1235 | RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7), |
| 1236 | }; |
| 1237 | static const unsigned int i2c2_a_mux[] = { |
| 1238 | SCL2_A_MARK, SDA2_A_MARK, |
| 1239 | }; |
| 1240 | static const unsigned int i2c2_b_pins[] = { |
| 1241 | /* SCL, SDA */ |
| 1242 | RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 30), |
| 1243 | }; |
| 1244 | static const unsigned int i2c2_b_mux[] = { |
| 1245 | SCL2_B_MARK, SDA2_B_MARK, |
| 1246 | }; |
| 1247 | static const unsigned int i2c3_a_pins[] = { |
| 1248 | /* SCL, SDA */ |
| 1249 | RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), |
| 1250 | }; |
| 1251 | static const unsigned int i2c3_a_mux[] = { |
| 1252 | SCL3_A_MARK, SDA3_A_MARK, |
| 1253 | }; |
| 1254 | static const unsigned int i2c3_b_pins[] = { |
| 1255 | /* SCL, SDA */ |
| 1256 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), |
| 1257 | }; |
| 1258 | static const unsigned int i2c3_b_mux[] = { |
| 1259 | SCL3_B_MARK, SDA3_B_MARK, |
| 1260 | }; |
| 1261 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 1262 | /* - MLB+ ------------------------------------------------------------------- */ |
| 1263 | static const unsigned int mlb_3pin_pins[] = { |
| 1264 | RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 7), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1265 | }; |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 1266 | static const unsigned int mlb_3pin_mux[] = { |
| 1267 | MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK, |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1268 | }; |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 1269 | |
| 1270 | /* - MMC ------------------------------------------------------------------- */ |
| 1271 | static const unsigned int mmc_data_pins[] = { |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1272 | /* D[0:7] */ |
| 1273 | RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), |
| 1274 | RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), |
| 1275 | RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7), |
| 1276 | RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), |
| 1277 | }; |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 1278 | static const unsigned int mmc_data_mux[] = { |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1279 | MMC_D0_MARK, MMC_D1_MARK, |
| 1280 | MMC_D2_MARK, MMC_D3_MARK, |
| 1281 | MMC_D4_MARK, MMC_D5_MARK, |
| 1282 | MMC_D6_MARK, MMC_D7_MARK, |
| 1283 | }; |
| 1284 | static const unsigned int mmc_ctrl_pins[] = { |
| 1285 | /* CLK, CMD */ |
| 1286 | RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0), |
| 1287 | }; |
| 1288 | static const unsigned int mmc_ctrl_mux[] = { |
| 1289 | MMC_CLK_MARK, MMC_CMD_MARK, |
| 1290 | }; |
| 1291 | |
Marek Vasut | 88e81ec | 2019-03-04 22:39:51 +0100 | [diff] [blame] | 1292 | /* - MSIOF0 ----------------------------------------------------------------- */ |
| 1293 | static const unsigned int msiof0_clk_pins[] = { |
| 1294 | /* SCK */ |
| 1295 | RCAR_GP_PIN(4, 12), |
| 1296 | }; |
| 1297 | |
| 1298 | static const unsigned int msiof0_clk_mux[] = { |
| 1299 | MSIOF0_SCK_MARK, |
| 1300 | }; |
| 1301 | |
| 1302 | static const unsigned int msiof0_sync_pins[] = { |
| 1303 | /* SYNC */ |
| 1304 | RCAR_GP_PIN(4, 13), |
| 1305 | }; |
| 1306 | |
| 1307 | static const unsigned int msiof0_sync_mux[] = { |
| 1308 | MSIOF0_SYNC_MARK, |
| 1309 | }; |
| 1310 | |
| 1311 | static const unsigned int msiof0_ss1_pins[] = { |
| 1312 | /* SS1 */ |
| 1313 | RCAR_GP_PIN(4, 20), |
| 1314 | }; |
| 1315 | |
| 1316 | static const unsigned int msiof0_ss1_mux[] = { |
| 1317 | MSIOF0_SS1_MARK, |
| 1318 | }; |
| 1319 | |
| 1320 | static const unsigned int msiof0_ss2_pins[] = { |
| 1321 | /* SS2 */ |
| 1322 | RCAR_GP_PIN(4, 21), |
| 1323 | }; |
| 1324 | |
| 1325 | static const unsigned int msiof0_ss2_mux[] = { |
| 1326 | MSIOF0_SS2_MARK, |
| 1327 | }; |
| 1328 | |
| 1329 | static const unsigned int msiof0_txd_pins[] = { |
| 1330 | /* TXD */ |
| 1331 | RCAR_GP_PIN(4, 14), |
| 1332 | }; |
| 1333 | |
| 1334 | static const unsigned int msiof0_txd_mux[] = { |
| 1335 | MSIOF0_TXD_MARK, |
| 1336 | }; |
| 1337 | |
| 1338 | static const unsigned int msiof0_rxd_pins[] = { |
| 1339 | /* RXD */ |
| 1340 | RCAR_GP_PIN(4, 15), |
| 1341 | }; |
| 1342 | |
| 1343 | static const unsigned int msiof0_rxd_mux[] = { |
| 1344 | MSIOF0_RXD_MARK, |
| 1345 | }; |
| 1346 | |
| 1347 | /* - MSIOF1 ----------------------------------------------------------------- */ |
| 1348 | static const unsigned int msiof1_clk_pins[] = { |
| 1349 | /* SCK */ |
| 1350 | RCAR_GP_PIN(4, 16), |
| 1351 | }; |
| 1352 | |
| 1353 | static const unsigned int msiof1_clk_mux[] = { |
| 1354 | MSIOF1_SCK_MARK, |
| 1355 | }; |
| 1356 | |
| 1357 | static const unsigned int msiof1_sync_pins[] = { |
| 1358 | /* SYNC */ |
| 1359 | RCAR_GP_PIN(4, 19), |
| 1360 | }; |
| 1361 | |
| 1362 | static const unsigned int msiof1_sync_mux[] = { |
| 1363 | MSIOF1_SYNC_MARK, |
| 1364 | }; |
| 1365 | |
| 1366 | static const unsigned int msiof1_ss1_pins[] = { |
| 1367 | /* SS1 */ |
| 1368 | RCAR_GP_PIN(4, 25), |
| 1369 | }; |
| 1370 | |
| 1371 | static const unsigned int msiof1_ss1_mux[] = { |
| 1372 | MSIOF1_SS1_MARK, |
| 1373 | }; |
| 1374 | |
| 1375 | static const unsigned int msiof1_ss2_pins[] = { |
| 1376 | /* SS2 */ |
| 1377 | RCAR_GP_PIN(4, 22), |
| 1378 | }; |
| 1379 | |
| 1380 | static const unsigned int msiof1_ss2_mux[] = { |
| 1381 | MSIOF1_SS2_MARK, |
| 1382 | }; |
| 1383 | |
| 1384 | static const unsigned int msiof1_txd_pins[] = { |
| 1385 | /* TXD */ |
| 1386 | RCAR_GP_PIN(4, 17), |
| 1387 | }; |
| 1388 | |
| 1389 | static const unsigned int msiof1_txd_mux[] = { |
| 1390 | MSIOF1_TXD_MARK, |
| 1391 | }; |
| 1392 | |
| 1393 | static const unsigned int msiof1_rxd_pins[] = { |
| 1394 | /* RXD */ |
| 1395 | RCAR_GP_PIN(4, 18), |
| 1396 | }; |
| 1397 | |
| 1398 | static const unsigned int msiof1_rxd_mux[] = { |
| 1399 | MSIOF1_RXD_MARK, |
| 1400 | }; |
| 1401 | |
| 1402 | /* - MSIOF2 ----------------------------------------------------------------- */ |
| 1403 | static const unsigned int msiof2_clk_pins[] = { |
| 1404 | /* SCK */ |
| 1405 | RCAR_GP_PIN(0, 3), |
| 1406 | }; |
| 1407 | |
| 1408 | static const unsigned int msiof2_clk_mux[] = { |
| 1409 | MSIOF2_SCK_MARK, |
| 1410 | }; |
| 1411 | |
| 1412 | static const unsigned int msiof2_sync_a_pins[] = { |
| 1413 | /* SYNC */ |
| 1414 | RCAR_GP_PIN(0, 6), |
| 1415 | }; |
| 1416 | |
| 1417 | static const unsigned int msiof2_sync_a_mux[] = { |
| 1418 | MSIOF2_SYNC_A_MARK, |
| 1419 | }; |
| 1420 | |
| 1421 | static const unsigned int msiof2_sync_b_pins[] = { |
| 1422 | /* SYNC */ |
| 1423 | RCAR_GP_PIN(0, 2), |
| 1424 | }; |
| 1425 | |
| 1426 | static const unsigned int msiof2_sync_b_mux[] = { |
| 1427 | MSIOF2_SYNC_B_MARK, |
| 1428 | }; |
| 1429 | |
| 1430 | static const unsigned int msiof2_ss1_pins[] = { |
| 1431 | /* SS1 */ |
| 1432 | RCAR_GP_PIN(0, 7), |
| 1433 | }; |
| 1434 | |
| 1435 | static const unsigned int msiof2_ss1_mux[] = { |
| 1436 | MSIOF2_SS1_MARK, |
| 1437 | }; |
| 1438 | |
| 1439 | static const unsigned int msiof2_ss2_pins[] = { |
| 1440 | /* SS2 */ |
| 1441 | RCAR_GP_PIN(0, 8), |
| 1442 | }; |
| 1443 | |
| 1444 | static const unsigned int msiof2_ss2_mux[] = { |
| 1445 | MSIOF2_SS2_MARK, |
| 1446 | }; |
| 1447 | |
| 1448 | static const unsigned int msiof2_txd_pins[] = { |
| 1449 | /* TXD */ |
| 1450 | RCAR_GP_PIN(0, 4), |
| 1451 | }; |
| 1452 | |
| 1453 | static const unsigned int msiof2_txd_mux[] = { |
| 1454 | MSIOF2_TXD_MARK, |
| 1455 | }; |
| 1456 | |
| 1457 | static const unsigned int msiof2_rxd_pins[] = { |
| 1458 | /* RXD */ |
| 1459 | RCAR_GP_PIN(0, 5), |
| 1460 | }; |
| 1461 | |
| 1462 | static const unsigned int msiof2_rxd_mux[] = { |
| 1463 | MSIOF2_RXD_MARK, |
| 1464 | }; |
| 1465 | |
| 1466 | /* - MSIOF3 ----------------------------------------------------------------- */ |
| 1467 | static const unsigned int msiof3_clk_a_pins[] = { |
| 1468 | /* SCK */ |
| 1469 | RCAR_GP_PIN(2, 24), |
| 1470 | }; |
| 1471 | |
| 1472 | static const unsigned int msiof3_clk_a_mux[] = { |
| 1473 | MSIOF3_SCK_A_MARK, |
| 1474 | }; |
| 1475 | |
| 1476 | static const unsigned int msiof3_sync_a_pins[] = { |
| 1477 | /* SYNC */ |
| 1478 | RCAR_GP_PIN(2, 21), |
| 1479 | }; |
| 1480 | |
| 1481 | static const unsigned int msiof3_sync_a_mux[] = { |
| 1482 | MSIOF3_SYNC_A_MARK, |
| 1483 | }; |
| 1484 | |
| 1485 | static const unsigned int msiof3_ss1_a_pins[] = { |
| 1486 | /* SS1 */ |
| 1487 | RCAR_GP_PIN(2, 14), |
| 1488 | }; |
| 1489 | |
| 1490 | static const unsigned int msiof3_ss1_a_mux[] = { |
| 1491 | MSIOF3_SS1_A_MARK, |
| 1492 | }; |
| 1493 | |
| 1494 | static const unsigned int msiof3_ss2_a_pins[] = { |
| 1495 | /* SS2 */ |
| 1496 | RCAR_GP_PIN(2, 10), |
| 1497 | }; |
| 1498 | |
| 1499 | static const unsigned int msiof3_ss2_a_mux[] = { |
| 1500 | MSIOF3_SS2_A_MARK, |
| 1501 | }; |
| 1502 | |
| 1503 | static const unsigned int msiof3_txd_a_pins[] = { |
| 1504 | /* TXD */ |
| 1505 | RCAR_GP_PIN(2, 22), |
| 1506 | }; |
| 1507 | |
| 1508 | static const unsigned int msiof3_txd_a_mux[] = { |
| 1509 | MSIOF3_TXD_A_MARK, |
| 1510 | }; |
| 1511 | |
| 1512 | static const unsigned int msiof3_rxd_a_pins[] = { |
| 1513 | /* RXD */ |
| 1514 | RCAR_GP_PIN(2, 23), |
| 1515 | }; |
| 1516 | |
| 1517 | static const unsigned int msiof3_rxd_a_mux[] = { |
| 1518 | MSIOF3_RXD_A_MARK, |
| 1519 | }; |
| 1520 | |
| 1521 | static const unsigned int msiof3_clk_b_pins[] = { |
| 1522 | /* SCK */ |
| 1523 | RCAR_GP_PIN(1, 8), |
| 1524 | }; |
| 1525 | |
| 1526 | static const unsigned int msiof3_clk_b_mux[] = { |
| 1527 | MSIOF3_SCK_B_MARK, |
| 1528 | }; |
| 1529 | |
| 1530 | static const unsigned int msiof3_sync_b_pins[] = { |
| 1531 | /* SYNC */ |
| 1532 | RCAR_GP_PIN(1, 9), |
| 1533 | }; |
| 1534 | |
| 1535 | static const unsigned int msiof3_sync_b_mux[] = { |
| 1536 | MSIOF3_SYNC_B_MARK, |
| 1537 | }; |
| 1538 | |
| 1539 | static const unsigned int msiof3_ss1_b_pins[] = { |
| 1540 | /* SS1 */ |
| 1541 | RCAR_GP_PIN(1, 6), |
| 1542 | }; |
| 1543 | |
| 1544 | static const unsigned int msiof3_ss1_b_mux[] = { |
| 1545 | MSIOF3_SS1_B_MARK, |
| 1546 | }; |
| 1547 | |
| 1548 | static const unsigned int msiof3_ss2_b_pins[] = { |
| 1549 | /* SS2 */ |
| 1550 | RCAR_GP_PIN(1, 7), |
| 1551 | }; |
| 1552 | |
| 1553 | static const unsigned int msiof3_ss2_b_mux[] = { |
| 1554 | MSIOF3_SS2_B_MARK, |
| 1555 | }; |
| 1556 | |
| 1557 | static const unsigned int msiof3_txd_b_pins[] = { |
| 1558 | /* TXD */ |
| 1559 | RCAR_GP_PIN(1, 0), |
| 1560 | }; |
| 1561 | |
| 1562 | static const unsigned int msiof3_txd_b_mux[] = { |
| 1563 | MSIOF3_TXD_B_MARK, |
| 1564 | }; |
| 1565 | |
| 1566 | static const unsigned int msiof3_rxd_b_pins[] = { |
| 1567 | /* RXD */ |
| 1568 | RCAR_GP_PIN(1, 1), |
| 1569 | }; |
| 1570 | |
| 1571 | static const unsigned int msiof3_rxd_b_mux[] = { |
| 1572 | MSIOF3_RXD_B_MARK, |
| 1573 | }; |
| 1574 | |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 1575 | /* - PWM0 ------------------------------------------------------------------ */ |
| 1576 | static const unsigned int pwm0_a_pins[] = { |
| 1577 | /* PWM */ |
| 1578 | RCAR_GP_PIN(2, 1), |
| 1579 | }; |
| 1580 | |
| 1581 | static const unsigned int pwm0_a_mux[] = { |
| 1582 | PWM0_A_MARK, |
| 1583 | }; |
| 1584 | |
| 1585 | static const unsigned int pwm0_b_pins[] = { |
| 1586 | /* PWM */ |
| 1587 | RCAR_GP_PIN(1, 18), |
| 1588 | }; |
| 1589 | |
| 1590 | static const unsigned int pwm0_b_mux[] = { |
| 1591 | PWM0_B_MARK, |
| 1592 | }; |
| 1593 | |
| 1594 | static const unsigned int pwm0_c_pins[] = { |
| 1595 | /* PWM */ |
| 1596 | RCAR_GP_PIN(2, 29), |
| 1597 | }; |
| 1598 | |
| 1599 | static const unsigned int pwm0_c_mux[] = { |
| 1600 | PWM0_C_MARK, |
| 1601 | }; |
| 1602 | |
| 1603 | /* - PWM1 ------------------------------------------------------------------ */ |
| 1604 | static const unsigned int pwm1_a_pins[] = { |
| 1605 | /* PWM */ |
| 1606 | RCAR_GP_PIN(2, 2), |
| 1607 | }; |
| 1608 | |
| 1609 | static const unsigned int pwm1_a_mux[] = { |
| 1610 | PWM1_A_MARK, |
| 1611 | }; |
| 1612 | |
| 1613 | static const unsigned int pwm1_b_pins[] = { |
| 1614 | /* PWM */ |
| 1615 | RCAR_GP_PIN(1, 19), |
| 1616 | }; |
| 1617 | |
| 1618 | static const unsigned int pwm1_b_mux[] = { |
| 1619 | PWM1_B_MARK, |
| 1620 | }; |
| 1621 | |
| 1622 | static const unsigned int pwm1_c_pins[] = { |
| 1623 | /* PWM */ |
| 1624 | RCAR_GP_PIN(2, 30), |
| 1625 | }; |
| 1626 | |
| 1627 | static const unsigned int pwm1_c_mux[] = { |
| 1628 | PWM1_C_MARK, |
| 1629 | }; |
| 1630 | |
| 1631 | /* - PWM2 ------------------------------------------------------------------ */ |
| 1632 | static const unsigned int pwm2_a_pins[] = { |
| 1633 | /* PWM */ |
| 1634 | RCAR_GP_PIN(2, 3), |
| 1635 | }; |
| 1636 | |
| 1637 | static const unsigned int pwm2_a_mux[] = { |
| 1638 | PWM2_A_MARK, |
| 1639 | }; |
| 1640 | |
| 1641 | static const unsigned int pwm2_b_pins[] = { |
| 1642 | /* PWM */ |
| 1643 | RCAR_GP_PIN(1, 22), |
| 1644 | }; |
| 1645 | |
| 1646 | static const unsigned int pwm2_b_mux[] = { |
| 1647 | PWM2_B_MARK, |
| 1648 | }; |
| 1649 | |
| 1650 | static const unsigned int pwm2_c_pins[] = { |
| 1651 | /* PWM */ |
| 1652 | RCAR_GP_PIN(2, 31), |
| 1653 | }; |
| 1654 | |
| 1655 | static const unsigned int pwm2_c_mux[] = { |
| 1656 | PWM2_C_MARK, |
| 1657 | }; |
| 1658 | |
| 1659 | /* - PWM3 ------------------------------------------------------------------ */ |
| 1660 | static const unsigned int pwm3_a_pins[] = { |
| 1661 | /* PWM */ |
| 1662 | RCAR_GP_PIN(2, 4), |
| 1663 | }; |
| 1664 | |
| 1665 | static const unsigned int pwm3_a_mux[] = { |
| 1666 | PWM3_A_MARK, |
| 1667 | }; |
| 1668 | |
| 1669 | static const unsigned int pwm3_b_pins[] = { |
| 1670 | /* PWM */ |
| 1671 | RCAR_GP_PIN(1, 27), |
| 1672 | }; |
| 1673 | |
| 1674 | static const unsigned int pwm3_b_mux[] = { |
| 1675 | PWM3_B_MARK, |
| 1676 | }; |
| 1677 | |
| 1678 | static const unsigned int pwm3_c_pins[] = { |
| 1679 | /* PWM */ |
| 1680 | RCAR_GP_PIN(4, 0), |
| 1681 | }; |
| 1682 | |
| 1683 | static const unsigned int pwm3_c_mux[] = { |
| 1684 | PWM3_C_MARK, |
| 1685 | }; |
| 1686 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 1687 | /* - QSPI0 ------------------------------------------------------------------ */ |
| 1688 | static const unsigned int qspi0_ctrl_pins[] = { |
| 1689 | /* QSPI0_SPCLK, QSPI0_SSL */ |
| 1690 | RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 5), |
| 1691 | }; |
| 1692 | static const unsigned int qspi0_ctrl_mux[] = { |
| 1693 | QSPI0_SPCLK_MARK, QSPI0_SSL_MARK, |
| 1694 | }; |
| 1695 | /* - QSPI1 ------------------------------------------------------------------ */ |
| 1696 | static const unsigned int qspi1_ctrl_pins[] = { |
| 1697 | /* QSPI1_SPCLK, QSPI1_SSL */ |
| 1698 | RCAR_GP_PIN(6, 6), RCAR_GP_PIN(6, 11), |
| 1699 | }; |
| 1700 | static const unsigned int qspi1_ctrl_mux[] = { |
| 1701 | QSPI1_SPCLK_MARK, QSPI1_SSL_MARK, |
| 1702 | }; |
| 1703 | |
| 1704 | /* - RPC -------------------------------------------------------------------- */ |
| 1705 | static const unsigned int rpc_clk_pins[] = { |
| 1706 | /* Octal-SPI flash: C/SCLK */ |
| 1707 | /* HyperFlash: CK, CK# */ |
| 1708 | RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 6), |
| 1709 | }; |
| 1710 | static const unsigned int rpc_clk_mux[] = { |
| 1711 | QSPI0_SPCLK_MARK, QSPI1_SPCLK_MARK, |
| 1712 | }; |
| 1713 | static const unsigned int rpc_ctrl_pins[] = { |
| 1714 | /* Octal-SPI flash: S#/CS, DQS */ |
| 1715 | /* HyperFlash: CS#, RDS */ |
| 1716 | RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 11), |
| 1717 | }; |
| 1718 | static const unsigned int rpc_ctrl_mux[] = { |
| 1719 | QSPI0_SSL_MARK, QSPI1_SSL_MARK, |
| 1720 | }; |
| 1721 | static const unsigned int rpc_data_pins[] = { |
| 1722 | /* DQ[0:7] */ |
| 1723 | RCAR_GP_PIN(6, 1), RCAR_GP_PIN(6, 2), |
| 1724 | RCAR_GP_PIN(6, 3), RCAR_GP_PIN(6, 4), |
| 1725 | RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 8), |
| 1726 | RCAR_GP_PIN(6, 9), RCAR_GP_PIN(6, 10), |
| 1727 | }; |
| 1728 | static const unsigned int rpc_data_mux[] = { |
| 1729 | QSPI0_MOSI_IO0_MARK, QSPI0_MISO_IO1_MARK, |
| 1730 | QSPI0_IO2_MARK, QSPI0_IO3_MARK, |
| 1731 | QSPI1_MOSI_IO0_MARK, QSPI1_MISO_IO1_MARK, |
| 1732 | QSPI1_IO2_MARK, QSPI1_IO3_MARK, |
| 1733 | }; |
| 1734 | static const unsigned int rpc_reset_pins[] = { |
| 1735 | /* RPC_RESET# */ |
| 1736 | RCAR_GP_PIN(6, 12), |
| 1737 | }; |
| 1738 | static const unsigned int rpc_reset_mux[] = { |
| 1739 | RPC_RESET_N_MARK, |
| 1740 | }; |
| 1741 | static const unsigned int rpc_int_pins[] = { |
| 1742 | /* RPC_INT# */ |
| 1743 | RCAR_GP_PIN(6, 13), |
| 1744 | }; |
| 1745 | static const unsigned int rpc_int_mux[] = { |
| 1746 | RPC_INT_N_MARK, |
| 1747 | }; |
| 1748 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1749 | /* - SCIF0 ------------------------------------------------------------------ */ |
| 1750 | static const unsigned int scif0_data_a_pins[] = { |
| 1751 | /* RX, TX */ |
| 1752 | RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21), |
| 1753 | }; |
| 1754 | static const unsigned int scif0_data_a_mux[] = { |
| 1755 | RX0_A_MARK, TX0_A_MARK, |
| 1756 | }; |
| 1757 | static const unsigned int scif0_clk_a_pins[] = { |
| 1758 | /* SCK */ |
| 1759 | RCAR_GP_PIN(4, 19), |
| 1760 | }; |
| 1761 | static const unsigned int scif0_clk_a_mux[] = { |
| 1762 | SCK0_A_MARK, |
| 1763 | }; |
| 1764 | static const unsigned int scif0_data_b_pins[] = { |
| 1765 | /* RX, TX */ |
| 1766 | RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 28), |
| 1767 | }; |
| 1768 | static const unsigned int scif0_data_b_mux[] = { |
| 1769 | RX0_B_MARK, TX0_B_MARK, |
| 1770 | }; |
| 1771 | static const unsigned int scif0_clk_b_pins[] = { |
| 1772 | /* SCK */ |
| 1773 | RCAR_GP_PIN(5, 2), |
| 1774 | }; |
| 1775 | static const unsigned int scif0_clk_b_mux[] = { |
| 1776 | SCK0_B_MARK, |
| 1777 | }; |
| 1778 | static const unsigned int scif0_ctrl_pins[] = { |
| 1779 | /* RTS, CTS */ |
| 1780 | RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 23), |
| 1781 | }; |
| 1782 | static const unsigned int scif0_ctrl_mux[] = { |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 1783 | RTS0_N_MARK, CTS0_N_MARK, |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1784 | }; |
| 1785 | /* - SCIF1 ------------------------------------------------------------------ */ |
| 1786 | static const unsigned int scif1_data_a_pins[] = { |
| 1787 | /* RX, TX */ |
| 1788 | RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24), |
| 1789 | }; |
| 1790 | static const unsigned int scif1_data_a_mux[] = { |
| 1791 | RX1_A_MARK, TX1_A_MARK, |
| 1792 | }; |
| 1793 | static const unsigned int scif1_clk_a_pins[] = { |
| 1794 | /* SCK */ |
| 1795 | RCAR_GP_PIN(4, 22), |
| 1796 | }; |
| 1797 | static const unsigned int scif1_clk_a_mux[] = { |
| 1798 | SCK1_A_MARK, |
| 1799 | }; |
| 1800 | static const unsigned int scif1_data_b_pins[] = { |
| 1801 | /* RX, TX */ |
| 1802 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 28), |
| 1803 | }; |
| 1804 | static const unsigned int scif1_data_b_mux[] = { |
| 1805 | RX1_B_MARK, TX1_B_MARK, |
| 1806 | }; |
| 1807 | static const unsigned int scif1_clk_b_pins[] = { |
| 1808 | /* SCK */ |
| 1809 | RCAR_GP_PIN(2, 25), |
| 1810 | }; |
| 1811 | static const unsigned int scif1_clk_b_mux[] = { |
| 1812 | SCK1_B_MARK, |
| 1813 | }; |
| 1814 | static const unsigned int scif1_ctrl_pins[] = { |
| 1815 | /* RTS, CTS */ |
| 1816 | RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 10), |
| 1817 | }; |
| 1818 | static const unsigned int scif1_ctrl_mux[] = { |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 1819 | RTS1_N_MARK, CTS1_N_MARK, |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 1820 | }; |
| 1821 | |
| 1822 | /* - SCIF2 ------------------------------------------------------------------ */ |
| 1823 | static const unsigned int scif2_data_pins[] = { |
| 1824 | /* RX, TX */ |
| 1825 | RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27), |
| 1826 | }; |
| 1827 | static const unsigned int scif2_data_mux[] = { |
| 1828 | RX2_MARK, TX2_MARK, |
| 1829 | }; |
| 1830 | static const unsigned int scif2_clk_pins[] = { |
| 1831 | /* SCK */ |
| 1832 | RCAR_GP_PIN(4, 25), |
| 1833 | }; |
| 1834 | static const unsigned int scif2_clk_mux[] = { |
| 1835 | SCK2_MARK, |
| 1836 | }; |
| 1837 | /* - SCIF3 ------------------------------------------------------------------ */ |
| 1838 | static const unsigned int scif3_data_a_pins[] = { |
| 1839 | /* RX, TX */ |
| 1840 | RCAR_GP_PIN(2, 31), RCAR_GP_PIN(4, 00), |
| 1841 | }; |
| 1842 | static const unsigned int scif3_data_a_mux[] = { |
| 1843 | RX3_A_MARK, TX3_A_MARK, |
| 1844 | }; |
| 1845 | static const unsigned int scif3_clk_a_pins[] = { |
| 1846 | /* SCK */ |
| 1847 | RCAR_GP_PIN(2, 30), |
| 1848 | }; |
| 1849 | static const unsigned int scif3_clk_a_mux[] = { |
| 1850 | SCK3_A_MARK, |
| 1851 | }; |
| 1852 | static const unsigned int scif3_data_b_pins[] = { |
| 1853 | /* RX, TX */ |
| 1854 | RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31), |
| 1855 | }; |
| 1856 | static const unsigned int scif3_data_b_mux[] = { |
| 1857 | RX3_B_MARK, TX3_B_MARK, |
| 1858 | }; |
| 1859 | static const unsigned int scif3_clk_b_pins[] = { |
| 1860 | /* SCK */ |
| 1861 | RCAR_GP_PIN(1, 29), |
| 1862 | }; |
| 1863 | static const unsigned int scif3_clk_b_mux[] = { |
| 1864 | SCK3_B_MARK, |
| 1865 | }; |
| 1866 | /* - SCIF4 ------------------------------------------------------------------ */ |
| 1867 | static const unsigned int scif4_data_a_pins[] = { |
| 1868 | /* RX, TX */ |
| 1869 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), |
| 1870 | }; |
| 1871 | static const unsigned int scif4_data_a_mux[] = { |
| 1872 | RX4_A_MARK, TX4_A_MARK, |
| 1873 | }; |
| 1874 | static const unsigned int scif4_clk_a_pins[] = { |
| 1875 | /* SCK */ |
| 1876 | RCAR_GP_PIN(2, 6), |
| 1877 | }; |
| 1878 | static const unsigned int scif4_clk_a_mux[] = { |
| 1879 | SCK4_A_MARK, |
| 1880 | }; |
| 1881 | static const unsigned int scif4_data_b_pins[] = { |
| 1882 | /* RX, TX */ |
| 1883 | RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17), |
| 1884 | }; |
| 1885 | static const unsigned int scif4_data_b_mux[] = { |
| 1886 | RX4_B_MARK, TX4_B_MARK, |
| 1887 | }; |
| 1888 | static const unsigned int scif4_clk_b_pins[] = { |
| 1889 | /* SCK */ |
| 1890 | RCAR_GP_PIN(1, 15), |
| 1891 | }; |
| 1892 | static const unsigned int scif4_clk_b_mux[] = { |
| 1893 | SCK4_B_MARK, |
| 1894 | }; |
| 1895 | /* - SCIF5 ------------------------------------------------------------------ */ |
| 1896 | static const unsigned int scif5_data_a_pins[] = { |
| 1897 | /* RX, TX */ |
| 1898 | RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 8), |
| 1899 | }; |
| 1900 | static const unsigned int scif5_data_a_mux[] = { |
| 1901 | RX5_A_MARK, TX5_A_MARK, |
| 1902 | }; |
| 1903 | static const unsigned int scif5_clk_a_pins[] = { |
| 1904 | /* SCK */ |
| 1905 | RCAR_GP_PIN(0, 6), |
| 1906 | }; |
| 1907 | static const unsigned int scif5_clk_a_mux[] = { |
| 1908 | SCK5_A_MARK, |
| 1909 | }; |
| 1910 | static const unsigned int scif5_data_b_pins[] = { |
| 1911 | /* RX, TX */ |
| 1912 | RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5), |
| 1913 | }; |
| 1914 | static const unsigned int scif5_data_b_mux[] = { |
| 1915 | RX5_B_MARK, TX5_B_MARK, |
| 1916 | }; |
| 1917 | static const unsigned int scif5_clk_b_pins[] = { |
| 1918 | /* SCK */ |
| 1919 | RCAR_GP_PIN(1, 3), |
| 1920 | }; |
| 1921 | static const unsigned int scif5_clk_b_mux[] = { |
| 1922 | SCK5_B_MARK, |
| 1923 | }; |
| 1924 | /* - SCIF Clock ------------------------------------------------------------- */ |
| 1925 | static const unsigned int scif_clk_pins[] = { |
| 1926 | /* SCIF_CLK */ |
| 1927 | RCAR_GP_PIN(2, 27), |
| 1928 | }; |
| 1929 | static const unsigned int scif_clk_mux[] = { |
| 1930 | SCIF_CLK_MARK, |
| 1931 | }; |
| 1932 | |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 1933 | /* - SSI ---------------------------------------------------------------*/ |
| 1934 | static const unsigned int ssi3_data_pins[] = { |
| 1935 | /* SDATA */ |
| 1936 | RCAR_GP_PIN(4, 3), |
| 1937 | }; |
| 1938 | static const unsigned int ssi3_data_mux[] = { |
| 1939 | SSI_SDATA3_MARK, |
| 1940 | }; |
| 1941 | static const unsigned int ssi34_ctrl_pins[] = { |
| 1942 | /* SCK, WS */ |
| 1943 | RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 4), |
| 1944 | }; |
| 1945 | static const unsigned int ssi34_ctrl_mux[] = { |
| 1946 | SSI_SCK34_MARK, SSI_WS34_MARK, |
| 1947 | }; |
| 1948 | static const unsigned int ssi4_ctrl_a_pins[] = { |
| 1949 | /* SCK, WS */ |
| 1950 | RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 7), |
| 1951 | }; |
| 1952 | static const unsigned int ssi4_ctrl_a_mux[] = { |
| 1953 | SSI_SCK4_A_MARK, SSI_WS4_A_MARK, |
| 1954 | }; |
| 1955 | static const unsigned int ssi4_data_a_pins[] = { |
| 1956 | /* SDATA */ |
| 1957 | RCAR_GP_PIN(4, 6), |
| 1958 | }; |
| 1959 | static const unsigned int ssi4_data_a_mux[] = { |
| 1960 | SSI_SDATA4_A_MARK, |
| 1961 | }; |
| 1962 | static const unsigned int ssi4_ctrl_b_pins[] = { |
| 1963 | /* SCK, WS */ |
| 1964 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 20), |
| 1965 | }; |
| 1966 | static const unsigned int ssi4_ctrl_b_mux[] = { |
| 1967 | SSI_SCK4_B_MARK, SSI_WS4_B_MARK, |
| 1968 | }; |
| 1969 | static const unsigned int ssi4_data_b_pins[] = { |
| 1970 | /* SDATA */ |
| 1971 | RCAR_GP_PIN(2, 16), |
| 1972 | }; |
| 1973 | static const unsigned int ssi4_data_b_mux[] = { |
| 1974 | SSI_SDATA4_B_MARK, |
| 1975 | }; |
| 1976 | |
| 1977 | /* - USB0 ------------------------------------------------------------------- */ |
| 1978 | static const unsigned int usb0_pins[] = { |
| 1979 | /* PWEN, OVC */ |
| 1980 | RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), |
| 1981 | }; |
| 1982 | static const unsigned int usb0_mux[] = { |
| 1983 | USB0_PWEN_MARK, USB0_OVC_MARK, |
| 1984 | }; |
| 1985 | |
| 1986 | /* - VIN4 ------------------------------------------------------------------- */ |
| 1987 | static const unsigned int vin4_data18_pins[] = { |
| 1988 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), |
| 1989 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), |
| 1990 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), |
| 1991 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), |
| 1992 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), |
| 1993 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), |
| 1994 | RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), |
| 1995 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), |
| 1996 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), |
| 1997 | }; |
| 1998 | static const unsigned int vin4_data18_mux[] = { |
| 1999 | VI4_DATA2_MARK, VI4_DATA3_MARK, |
| 2000 | VI4_DATA4_MARK, VI4_DATA5_MARK, |
| 2001 | VI4_DATA6_MARK, VI4_DATA7_MARK, |
| 2002 | VI4_DATA10_MARK, VI4_DATA11_MARK, |
| 2003 | VI4_DATA12_MARK, VI4_DATA13_MARK, |
| 2004 | VI4_DATA14_MARK, VI4_DATA15_MARK, |
| 2005 | VI4_DATA18_MARK, VI4_DATA19_MARK, |
| 2006 | VI4_DATA20_MARK, VI4_DATA21_MARK, |
| 2007 | VI4_DATA22_MARK, VI4_DATA23_MARK, |
| 2008 | }; |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2009 | static const unsigned int vin4_data_pins[] = { |
| 2010 | RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), |
| 2011 | RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4), |
| 2012 | RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), |
| 2013 | RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), |
| 2014 | RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10), |
| 2015 | RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), |
| 2016 | RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), |
| 2017 | RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16), |
| 2018 | RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18), |
| 2019 | RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20), |
| 2020 | RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22), |
| 2021 | RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 24), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2022 | }; |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2023 | static const unsigned int vin4_data_mux[] = { |
| 2024 | VI4_DATA0_MARK, VI4_DATA1_MARK, |
| 2025 | VI4_DATA2_MARK, VI4_DATA3_MARK, |
| 2026 | VI4_DATA4_MARK, VI4_DATA5_MARK, |
| 2027 | VI4_DATA6_MARK, VI4_DATA7_MARK, |
| 2028 | VI4_DATA8_MARK, VI4_DATA9_MARK, |
| 2029 | VI4_DATA10_MARK, VI4_DATA11_MARK, |
| 2030 | VI4_DATA12_MARK, VI4_DATA13_MARK, |
| 2031 | VI4_DATA14_MARK, VI4_DATA15_MARK, |
| 2032 | VI4_DATA16_MARK, VI4_DATA17_MARK, |
| 2033 | VI4_DATA18_MARK, VI4_DATA19_MARK, |
| 2034 | VI4_DATA20_MARK, VI4_DATA21_MARK, |
| 2035 | VI4_DATA22_MARK, VI4_DATA23_MARK, |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2036 | }; |
| 2037 | static const unsigned int vin4_sync_pins[] = { |
| 2038 | /* HSYNC#, VSYNC# */ |
| 2039 | RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 25), |
| 2040 | }; |
| 2041 | static const unsigned int vin4_sync_mux[] = { |
| 2042 | VI4_HSYNC_N_MARK, VI4_VSYNC_N_MARK, |
| 2043 | }; |
| 2044 | static const unsigned int vin4_field_pins[] = { |
| 2045 | /* FIELD */ |
| 2046 | RCAR_GP_PIN(2, 27), |
| 2047 | }; |
| 2048 | static const unsigned int vin4_field_mux[] = { |
| 2049 | VI4_FIELD_MARK, |
| 2050 | }; |
| 2051 | static const unsigned int vin4_clkenb_pins[] = { |
| 2052 | /* CLKENB */ |
| 2053 | RCAR_GP_PIN(2, 28), |
| 2054 | }; |
| 2055 | static const unsigned int vin4_clkenb_mux[] = { |
| 2056 | VI4_CLKENB_MARK, |
| 2057 | }; |
| 2058 | static const unsigned int vin4_clk_pins[] = { |
| 2059 | /* CLK */ |
| 2060 | RCAR_GP_PIN(2, 0), |
| 2061 | }; |
| 2062 | static const unsigned int vin4_clk_mux[] = { |
| 2063 | VI4_CLK_MARK, |
| 2064 | }; |
| 2065 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2066 | static const struct sh_pfc_pin_group pinmux_groups[] = { |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2067 | SH_PFC_PIN_GROUP(audio_clk_a), |
| 2068 | SH_PFC_PIN_GROUP(audio_clk_b), |
| 2069 | SH_PFC_PIN_GROUP(audio_clkout), |
| 2070 | SH_PFC_PIN_GROUP(audio_clkout1), |
| 2071 | SH_PFC_PIN_GROUP(avb0_link), |
| 2072 | SH_PFC_PIN_GROUP(avb0_magic), |
| 2073 | SH_PFC_PIN_GROUP(avb0_phy_int), |
| 2074 | SH_PFC_PIN_GROUP_ALIAS(avb0_mdc, avb0_mdio), /* Deprecated */ |
| 2075 | SH_PFC_PIN_GROUP(avb0_mdio), |
| 2076 | SH_PFC_PIN_GROUP(avb0_mii), |
| 2077 | SH_PFC_PIN_GROUP(avb0_avtp_pps_a), |
| 2078 | SH_PFC_PIN_GROUP(avb0_avtp_match_a), |
| 2079 | SH_PFC_PIN_GROUP(avb0_avtp_capture_a), |
| 2080 | SH_PFC_PIN_GROUP(avb0_avtp_pps_b), |
| 2081 | SH_PFC_PIN_GROUP(avb0_avtp_match_b), |
| 2082 | SH_PFC_PIN_GROUP(avb0_avtp_capture_b), |
| 2083 | SH_PFC_PIN_GROUP(can0_data_a), |
| 2084 | SH_PFC_PIN_GROUP(can0_data_b), |
| 2085 | SH_PFC_PIN_GROUP(can1_data_a), |
| 2086 | SH_PFC_PIN_GROUP(can1_data_b), |
| 2087 | SH_PFC_PIN_GROUP(can_clk), |
| 2088 | SH_PFC_PIN_GROUP(canfd0_data), |
| 2089 | SH_PFC_PIN_GROUP(canfd1_data), |
| 2090 | SH_PFC_PIN_GROUP(du_rgb666), |
| 2091 | SH_PFC_PIN_GROUP(du_rgb888), |
| 2092 | SH_PFC_PIN_GROUP(du_clk_in_1), |
| 2093 | SH_PFC_PIN_GROUP(du_clk_out_0), |
| 2094 | SH_PFC_PIN_GROUP(du_sync), |
| 2095 | SH_PFC_PIN_GROUP(du_disp_cde), |
| 2096 | SH_PFC_PIN_GROUP(du_cde), |
| 2097 | SH_PFC_PIN_GROUP(du_disp), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2098 | SH_PFC_PIN_GROUP(i2c0), |
| 2099 | SH_PFC_PIN_GROUP(i2c1), |
| 2100 | SH_PFC_PIN_GROUP(i2c2_a), |
| 2101 | SH_PFC_PIN_GROUP(i2c2_b), |
| 2102 | SH_PFC_PIN_GROUP(i2c3_a), |
| 2103 | SH_PFC_PIN_GROUP(i2c3_b), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2104 | SH_PFC_PIN_GROUP(mlb_3pin), |
| 2105 | BUS_DATA_PIN_GROUP(mmc_data, 1), |
| 2106 | BUS_DATA_PIN_GROUP(mmc_data, 4), |
| 2107 | BUS_DATA_PIN_GROUP(mmc_data, 8), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2108 | SH_PFC_PIN_GROUP(mmc_ctrl), |
Marek Vasut | 88e81ec | 2019-03-04 22:39:51 +0100 | [diff] [blame] | 2109 | SH_PFC_PIN_GROUP(msiof0_clk), |
| 2110 | SH_PFC_PIN_GROUP(msiof0_sync), |
| 2111 | SH_PFC_PIN_GROUP(msiof0_ss1), |
| 2112 | SH_PFC_PIN_GROUP(msiof0_ss2), |
| 2113 | SH_PFC_PIN_GROUP(msiof0_txd), |
| 2114 | SH_PFC_PIN_GROUP(msiof0_rxd), |
| 2115 | SH_PFC_PIN_GROUP(msiof1_clk), |
| 2116 | SH_PFC_PIN_GROUP(msiof1_sync), |
| 2117 | SH_PFC_PIN_GROUP(msiof1_ss1), |
| 2118 | SH_PFC_PIN_GROUP(msiof1_ss2), |
| 2119 | SH_PFC_PIN_GROUP(msiof1_txd), |
| 2120 | SH_PFC_PIN_GROUP(msiof1_rxd), |
| 2121 | SH_PFC_PIN_GROUP(msiof2_clk), |
| 2122 | SH_PFC_PIN_GROUP(msiof2_sync_a), |
| 2123 | SH_PFC_PIN_GROUP(msiof2_sync_b), |
| 2124 | SH_PFC_PIN_GROUP(msiof2_ss1), |
| 2125 | SH_PFC_PIN_GROUP(msiof2_ss2), |
| 2126 | SH_PFC_PIN_GROUP(msiof2_txd), |
| 2127 | SH_PFC_PIN_GROUP(msiof2_rxd), |
| 2128 | SH_PFC_PIN_GROUP(msiof3_clk_a), |
| 2129 | SH_PFC_PIN_GROUP(msiof3_sync_a), |
| 2130 | SH_PFC_PIN_GROUP(msiof3_ss1_a), |
| 2131 | SH_PFC_PIN_GROUP(msiof3_ss2_a), |
| 2132 | SH_PFC_PIN_GROUP(msiof3_txd_a), |
| 2133 | SH_PFC_PIN_GROUP(msiof3_rxd_a), |
| 2134 | SH_PFC_PIN_GROUP(msiof3_clk_b), |
| 2135 | SH_PFC_PIN_GROUP(msiof3_sync_b), |
| 2136 | SH_PFC_PIN_GROUP(msiof3_ss1_b), |
| 2137 | SH_PFC_PIN_GROUP(msiof3_ss2_b), |
| 2138 | SH_PFC_PIN_GROUP(msiof3_txd_b), |
| 2139 | SH_PFC_PIN_GROUP(msiof3_rxd_b), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2140 | SH_PFC_PIN_GROUP(pwm0_a), |
| 2141 | SH_PFC_PIN_GROUP(pwm0_b), |
| 2142 | SH_PFC_PIN_GROUP(pwm0_c), |
| 2143 | SH_PFC_PIN_GROUP(pwm1_a), |
| 2144 | SH_PFC_PIN_GROUP(pwm1_b), |
| 2145 | SH_PFC_PIN_GROUP(pwm1_c), |
| 2146 | SH_PFC_PIN_GROUP(pwm2_a), |
| 2147 | SH_PFC_PIN_GROUP(pwm2_b), |
| 2148 | SH_PFC_PIN_GROUP(pwm2_c), |
| 2149 | SH_PFC_PIN_GROUP(pwm3_a), |
| 2150 | SH_PFC_PIN_GROUP(pwm3_b), |
| 2151 | SH_PFC_PIN_GROUP(pwm3_c), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2152 | SH_PFC_PIN_GROUP(qspi0_ctrl), |
| 2153 | SH_PFC_PIN_GROUP_SUBSET(qspi0_data2, rpc_data, 0, 2), |
| 2154 | SH_PFC_PIN_GROUP_SUBSET(qspi0_data4, rpc_data, 0, 4), |
| 2155 | SH_PFC_PIN_GROUP(qspi1_ctrl), |
| 2156 | SH_PFC_PIN_GROUP_SUBSET(qspi1_data2, rpc_data, 4, 2), |
| 2157 | SH_PFC_PIN_GROUP_SUBSET(qspi1_data4, rpc_data, 4, 4), |
| 2158 | BUS_DATA_PIN_GROUP(rpc_clk, 1), |
| 2159 | BUS_DATA_PIN_GROUP(rpc_clk, 2), |
| 2160 | SH_PFC_PIN_GROUP(rpc_ctrl), |
| 2161 | SH_PFC_PIN_GROUP(rpc_data), |
| 2162 | SH_PFC_PIN_GROUP(rpc_reset), |
| 2163 | SH_PFC_PIN_GROUP(rpc_int), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2164 | SH_PFC_PIN_GROUP(scif0_data_a), |
| 2165 | SH_PFC_PIN_GROUP(scif0_clk_a), |
| 2166 | SH_PFC_PIN_GROUP(scif0_data_b), |
| 2167 | SH_PFC_PIN_GROUP(scif0_clk_b), |
| 2168 | SH_PFC_PIN_GROUP(scif0_ctrl), |
| 2169 | SH_PFC_PIN_GROUP(scif1_data_a), |
| 2170 | SH_PFC_PIN_GROUP(scif1_clk_a), |
| 2171 | SH_PFC_PIN_GROUP(scif1_data_b), |
| 2172 | SH_PFC_PIN_GROUP(scif1_clk_b), |
| 2173 | SH_PFC_PIN_GROUP(scif1_ctrl), |
| 2174 | SH_PFC_PIN_GROUP(scif2_data), |
| 2175 | SH_PFC_PIN_GROUP(scif2_clk), |
| 2176 | SH_PFC_PIN_GROUP(scif3_data_a), |
| 2177 | SH_PFC_PIN_GROUP(scif3_clk_a), |
| 2178 | SH_PFC_PIN_GROUP(scif3_data_b), |
| 2179 | SH_PFC_PIN_GROUP(scif3_clk_b), |
| 2180 | SH_PFC_PIN_GROUP(scif4_data_a), |
| 2181 | SH_PFC_PIN_GROUP(scif4_clk_a), |
| 2182 | SH_PFC_PIN_GROUP(scif4_data_b), |
| 2183 | SH_PFC_PIN_GROUP(scif4_clk_b), |
| 2184 | SH_PFC_PIN_GROUP(scif5_data_a), |
| 2185 | SH_PFC_PIN_GROUP(scif5_clk_a), |
| 2186 | SH_PFC_PIN_GROUP(scif5_data_b), |
| 2187 | SH_PFC_PIN_GROUP(scif5_clk_b), |
| 2188 | SH_PFC_PIN_GROUP(scif_clk), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2189 | SH_PFC_PIN_GROUP(ssi3_data), |
| 2190 | SH_PFC_PIN_GROUP(ssi34_ctrl), |
| 2191 | SH_PFC_PIN_GROUP(ssi4_ctrl_a), |
| 2192 | SH_PFC_PIN_GROUP(ssi4_data_a), |
| 2193 | SH_PFC_PIN_GROUP(ssi4_ctrl_b), |
| 2194 | SH_PFC_PIN_GROUP(ssi4_data_b), |
| 2195 | SH_PFC_PIN_GROUP(usb0), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2196 | BUS_DATA_PIN_GROUP(vin4_data, 8), |
| 2197 | BUS_DATA_PIN_GROUP(vin4_data, 10), |
| 2198 | BUS_DATA_PIN_GROUP(vin4_data, 12), |
| 2199 | BUS_DATA_PIN_GROUP(vin4_data, 16), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2200 | SH_PFC_PIN_GROUP(vin4_data18), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2201 | BUS_DATA_PIN_GROUP(vin4_data, 20), |
| 2202 | BUS_DATA_PIN_GROUP(vin4_data, 24), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2203 | SH_PFC_PIN_GROUP(vin4_sync), |
| 2204 | SH_PFC_PIN_GROUP(vin4_field), |
| 2205 | SH_PFC_PIN_GROUP(vin4_clkenb), |
| 2206 | SH_PFC_PIN_GROUP(vin4_clk), |
| 2207 | }; |
| 2208 | |
| 2209 | static const char * const audio_clk_groups[] = { |
| 2210 | "audio_clk_a", |
| 2211 | "audio_clk_b", |
| 2212 | "audio_clkout", |
| 2213 | "audio_clkout1", |
| 2214 | }; |
| 2215 | |
| 2216 | static const char * const avb0_groups[] = { |
| 2217 | "avb0_link", |
| 2218 | "avb0_magic", |
| 2219 | "avb0_phy_int", |
| 2220 | "avb0_mdc", /* Deprecated, please use "avb0_mdio" instead */ |
| 2221 | "avb0_mdio", |
| 2222 | "avb0_mii", |
| 2223 | "avb0_avtp_pps_a", |
| 2224 | "avb0_avtp_match_a", |
| 2225 | "avb0_avtp_capture_a", |
| 2226 | "avb0_avtp_pps_b", |
| 2227 | "avb0_avtp_match_b", |
| 2228 | "avb0_avtp_capture_b", |
| 2229 | }; |
| 2230 | |
| 2231 | static const char * const can0_groups[] = { |
| 2232 | "can0_data_a", |
| 2233 | "can0_data_b", |
| 2234 | }; |
| 2235 | static const char * const can1_groups[] = { |
| 2236 | "can1_data_a", |
| 2237 | "can1_data_b", |
| 2238 | }; |
| 2239 | static const char * const can_clk_groups[] = { |
| 2240 | "can_clk", |
| 2241 | }; |
| 2242 | |
| 2243 | static const char * const canfd0_groups[] = { |
| 2244 | "canfd0_data", |
| 2245 | }; |
| 2246 | static const char * const canfd1_groups[] = { |
| 2247 | "canfd1_data", |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2248 | }; |
| 2249 | |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2250 | static const char * const du_groups[] = { |
| 2251 | "du_rgb666", |
| 2252 | "du_rgb888", |
| 2253 | "du_clk_in_1", |
| 2254 | "du_clk_out_0", |
| 2255 | "du_sync", |
| 2256 | "du_disp_cde", |
| 2257 | "du_cde", |
| 2258 | "du_disp", |
| 2259 | }; |
| 2260 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2261 | static const char * const i2c0_groups[] = { |
| 2262 | "i2c0", |
| 2263 | }; |
| 2264 | static const char * const i2c1_groups[] = { |
| 2265 | "i2c1", |
| 2266 | }; |
| 2267 | |
| 2268 | static const char * const i2c2_groups[] = { |
| 2269 | "i2c2_a", |
| 2270 | "i2c2_b", |
| 2271 | }; |
| 2272 | |
| 2273 | static const char * const i2c3_groups[] = { |
| 2274 | "i2c3_a", |
| 2275 | "i2c3_b", |
| 2276 | }; |
| 2277 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2278 | static const char * const mlb_3pin_groups[] = { |
| 2279 | "mlb_3pin", |
| 2280 | }; |
| 2281 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2282 | static const char * const mmc_groups[] = { |
| 2283 | "mmc_data1", |
| 2284 | "mmc_data4", |
| 2285 | "mmc_data8", |
| 2286 | "mmc_ctrl", |
| 2287 | }; |
| 2288 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2289 | static const char * const msiof0_groups[] = { |
| 2290 | "msiof0_clk", |
| 2291 | "msiof0_sync", |
| 2292 | "msiof0_ss1", |
| 2293 | "msiof0_ss2", |
| 2294 | "msiof0_txd", |
| 2295 | "msiof0_rxd", |
| 2296 | }; |
| 2297 | |
| 2298 | static const char * const msiof1_groups[] = { |
| 2299 | "msiof1_clk", |
| 2300 | "msiof1_sync", |
| 2301 | "msiof1_ss1", |
| 2302 | "msiof1_ss2", |
| 2303 | "msiof1_txd", |
| 2304 | "msiof1_rxd", |
| 2305 | }; |
| 2306 | |
| 2307 | static const char * const msiof2_groups[] = { |
| 2308 | "msiof2_clk", |
| 2309 | "msiof2_sync_a", |
| 2310 | "msiof2_sync_b", |
| 2311 | "msiof2_ss1", |
| 2312 | "msiof2_ss2", |
| 2313 | "msiof2_txd", |
| 2314 | "msiof2_rxd", |
| 2315 | }; |
| 2316 | |
| 2317 | static const char * const msiof3_groups[] = { |
| 2318 | "msiof3_clk_a", |
| 2319 | "msiof3_sync_a", |
| 2320 | "msiof3_ss1_a", |
| 2321 | "msiof3_ss2_a", |
| 2322 | "msiof3_txd_a", |
| 2323 | "msiof3_rxd_a", |
| 2324 | "msiof3_clk_b", |
| 2325 | "msiof3_sync_b", |
| 2326 | "msiof3_ss1_b", |
| 2327 | "msiof3_ss2_b", |
| 2328 | "msiof3_txd_b", |
| 2329 | "msiof3_rxd_b", |
| 2330 | }; |
| 2331 | |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2332 | static const char * const pwm0_groups[] = { |
| 2333 | "pwm0_a", |
| 2334 | "pwm0_b", |
| 2335 | "pwm0_c", |
| 2336 | }; |
| 2337 | |
| 2338 | static const char * const pwm1_groups[] = { |
| 2339 | "pwm1_a", |
| 2340 | "pwm1_b", |
| 2341 | "pwm1_c", |
| 2342 | }; |
| 2343 | |
| 2344 | static const char * const pwm2_groups[] = { |
| 2345 | "pwm2_a", |
| 2346 | "pwm2_b", |
| 2347 | "pwm2_c", |
| 2348 | }; |
| 2349 | |
| 2350 | static const char * const pwm3_groups[] = { |
| 2351 | "pwm3_a", |
| 2352 | "pwm3_b", |
| 2353 | "pwm3_c", |
| 2354 | }; |
| 2355 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2356 | static const char * const qspi0_groups[] = { |
| 2357 | "qspi0_ctrl", |
| 2358 | "qspi0_data2", |
| 2359 | "qspi0_data4", |
| 2360 | }; |
| 2361 | |
| 2362 | static const char * const qspi1_groups[] = { |
| 2363 | "qspi1_ctrl", |
| 2364 | "qspi1_data2", |
| 2365 | "qspi1_data4", |
| 2366 | }; |
| 2367 | |
| 2368 | static const char * const rpc_groups[] = { |
| 2369 | "rpc_clk1", |
| 2370 | "rpc_clk2", |
| 2371 | "rpc_ctrl", |
| 2372 | "rpc_data", |
| 2373 | "rpc_reset", |
| 2374 | "rpc_int", |
| 2375 | }; |
| 2376 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2377 | static const char * const scif0_groups[] = { |
| 2378 | "scif0_data_a", |
| 2379 | "scif0_clk_a", |
| 2380 | "scif0_data_b", |
| 2381 | "scif0_clk_b", |
| 2382 | "scif0_ctrl", |
| 2383 | }; |
| 2384 | |
| 2385 | static const char * const scif1_groups[] = { |
| 2386 | "scif1_data_a", |
| 2387 | "scif1_clk_a", |
| 2388 | "scif1_data_b", |
| 2389 | "scif1_clk_b", |
| 2390 | "scif1_ctrl", |
| 2391 | }; |
| 2392 | |
| 2393 | static const char * const scif2_groups[] = { |
| 2394 | "scif2_data", |
| 2395 | "scif2_clk", |
| 2396 | }; |
| 2397 | |
| 2398 | static const char * const scif3_groups[] = { |
| 2399 | "scif3_data_a", |
| 2400 | "scif3_clk_a", |
| 2401 | "scif3_data_b", |
| 2402 | "scif3_clk_b", |
| 2403 | }; |
| 2404 | |
| 2405 | static const char * const scif4_groups[] = { |
| 2406 | "scif4_data_a", |
| 2407 | "scif4_clk_a", |
| 2408 | "scif4_data_b", |
| 2409 | "scif4_clk_b", |
| 2410 | }; |
| 2411 | |
| 2412 | static const char * const scif5_groups[] = { |
| 2413 | "scif5_data_a", |
| 2414 | "scif5_clk_a", |
| 2415 | "scif5_data_b", |
| 2416 | "scif5_clk_b", |
| 2417 | }; |
| 2418 | |
| 2419 | static const char * const scif_clk_groups[] = { |
| 2420 | "scif_clk", |
| 2421 | }; |
| 2422 | |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2423 | static const char * const ssi_groups[] = { |
| 2424 | "ssi3_data", |
| 2425 | "ssi34_ctrl", |
| 2426 | "ssi4_ctrl_a", |
| 2427 | "ssi4_data_a", |
| 2428 | "ssi4_ctrl_b", |
| 2429 | "ssi4_data_b", |
| 2430 | }; |
| 2431 | |
| 2432 | static const char * const usb0_groups[] = { |
| 2433 | "usb0", |
| 2434 | }; |
| 2435 | |
| 2436 | static const char * const vin4_groups[] = { |
| 2437 | "vin4_data8", |
| 2438 | "vin4_data10", |
| 2439 | "vin4_data12", |
| 2440 | "vin4_data16", |
| 2441 | "vin4_data18", |
| 2442 | "vin4_data20", |
| 2443 | "vin4_data24", |
| 2444 | "vin4_sync", |
| 2445 | "vin4_field", |
| 2446 | "vin4_clkenb", |
| 2447 | "vin4_clk", |
| 2448 | }; |
| 2449 | |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2450 | static const struct sh_pfc_function pinmux_functions[] = { |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2451 | SH_PFC_FUNCTION(audio_clk), |
| 2452 | SH_PFC_FUNCTION(avb0), |
| 2453 | SH_PFC_FUNCTION(can0), |
| 2454 | SH_PFC_FUNCTION(can1), |
| 2455 | SH_PFC_FUNCTION(can_clk), |
| 2456 | SH_PFC_FUNCTION(canfd0), |
| 2457 | SH_PFC_FUNCTION(canfd1), |
| 2458 | SH_PFC_FUNCTION(du), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2459 | SH_PFC_FUNCTION(i2c0), |
| 2460 | SH_PFC_FUNCTION(i2c1), |
| 2461 | SH_PFC_FUNCTION(i2c2), |
| 2462 | SH_PFC_FUNCTION(i2c3), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2463 | SH_PFC_FUNCTION(mlb_3pin), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2464 | SH_PFC_FUNCTION(mmc), |
Marek Vasut | 88e81ec | 2019-03-04 22:39:51 +0100 | [diff] [blame] | 2465 | SH_PFC_FUNCTION(msiof0), |
| 2466 | SH_PFC_FUNCTION(msiof1), |
| 2467 | SH_PFC_FUNCTION(msiof2), |
| 2468 | SH_PFC_FUNCTION(msiof3), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2469 | SH_PFC_FUNCTION(pwm0), |
| 2470 | SH_PFC_FUNCTION(pwm1), |
| 2471 | SH_PFC_FUNCTION(pwm2), |
| 2472 | SH_PFC_FUNCTION(pwm3), |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2473 | SH_PFC_FUNCTION(qspi0), |
| 2474 | SH_PFC_FUNCTION(qspi1), |
| 2475 | SH_PFC_FUNCTION(rpc), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2476 | SH_PFC_FUNCTION(scif0), |
| 2477 | SH_PFC_FUNCTION(scif1), |
| 2478 | SH_PFC_FUNCTION(scif2), |
| 2479 | SH_PFC_FUNCTION(scif3), |
| 2480 | SH_PFC_FUNCTION(scif4), |
| 2481 | SH_PFC_FUNCTION(scif5), |
| 2482 | SH_PFC_FUNCTION(scif_clk), |
Marek Vasut | eb13e0f | 2018-06-10 16:05:48 +0200 | [diff] [blame] | 2483 | SH_PFC_FUNCTION(ssi), |
| 2484 | SH_PFC_FUNCTION(usb0), |
| 2485 | SH_PFC_FUNCTION(vin4), |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2486 | }; |
| 2487 | |
| 2488 | static const struct pinmux_cfg_reg pinmux_config_regs[] = { |
| 2489 | #define F_(x, y) FN_##y |
| 2490 | #define FM(x) FN_##x |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2491 | { PINMUX_CFG_REG_VAR("GPSR0", 0xe6060100, 32, |
| 2492 | GROUP(-23, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 2493 | GROUP( |
| 2494 | /* GP0_31_9 RESERVED */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2495 | GP_0_8_FN, GPSR0_8, |
| 2496 | GP_0_7_FN, GPSR0_7, |
| 2497 | GP_0_6_FN, GPSR0_6, |
| 2498 | GP_0_5_FN, GPSR0_5, |
| 2499 | GP_0_4_FN, GPSR0_4, |
| 2500 | GP_0_3_FN, GPSR0_3, |
| 2501 | GP_0_2_FN, GPSR0_2, |
| 2502 | GP_0_1_FN, GPSR0_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2503 | GP_0_0_FN, GPSR0_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2504 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2505 | { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2506 | GP_1_31_FN, GPSR1_31, |
| 2507 | GP_1_30_FN, GPSR1_30, |
| 2508 | GP_1_29_FN, GPSR1_29, |
| 2509 | GP_1_28_FN, GPSR1_28, |
| 2510 | GP_1_27_FN, GPSR1_27, |
| 2511 | GP_1_26_FN, GPSR1_26, |
| 2512 | GP_1_25_FN, GPSR1_25, |
| 2513 | GP_1_24_FN, GPSR1_24, |
| 2514 | GP_1_23_FN, GPSR1_23, |
| 2515 | GP_1_22_FN, GPSR1_22, |
| 2516 | GP_1_21_FN, GPSR1_21, |
| 2517 | GP_1_20_FN, GPSR1_20, |
| 2518 | GP_1_19_FN, GPSR1_19, |
| 2519 | GP_1_18_FN, GPSR1_18, |
| 2520 | GP_1_17_FN, GPSR1_17, |
| 2521 | GP_1_16_FN, GPSR1_16, |
| 2522 | GP_1_15_FN, GPSR1_15, |
| 2523 | GP_1_14_FN, GPSR1_14, |
| 2524 | GP_1_13_FN, GPSR1_13, |
| 2525 | GP_1_12_FN, GPSR1_12, |
| 2526 | GP_1_11_FN, GPSR1_11, |
| 2527 | GP_1_10_FN, GPSR1_10, |
| 2528 | GP_1_9_FN, GPSR1_9, |
| 2529 | GP_1_8_FN, GPSR1_8, |
| 2530 | GP_1_7_FN, GPSR1_7, |
| 2531 | GP_1_6_FN, GPSR1_6, |
| 2532 | GP_1_5_FN, GPSR1_5, |
| 2533 | GP_1_4_FN, GPSR1_4, |
| 2534 | GP_1_3_FN, GPSR1_3, |
| 2535 | GP_1_2_FN, GPSR1_2, |
| 2536 | GP_1_1_FN, GPSR1_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2537 | GP_1_0_FN, GPSR1_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2538 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2539 | { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2540 | GP_2_31_FN, GPSR2_31, |
| 2541 | GP_2_30_FN, GPSR2_30, |
| 2542 | GP_2_29_FN, GPSR2_29, |
| 2543 | GP_2_28_FN, GPSR2_28, |
| 2544 | GP_2_27_FN, GPSR2_27, |
| 2545 | GP_2_26_FN, GPSR2_26, |
| 2546 | GP_2_25_FN, GPSR2_25, |
| 2547 | GP_2_24_FN, GPSR2_24, |
| 2548 | GP_2_23_FN, GPSR2_23, |
| 2549 | GP_2_22_FN, GPSR2_22, |
| 2550 | GP_2_21_FN, GPSR2_21, |
| 2551 | GP_2_20_FN, GPSR2_20, |
| 2552 | GP_2_19_FN, GPSR2_19, |
| 2553 | GP_2_18_FN, GPSR2_18, |
| 2554 | GP_2_17_FN, GPSR2_17, |
| 2555 | GP_2_16_FN, GPSR2_16, |
| 2556 | GP_2_15_FN, GPSR2_15, |
| 2557 | GP_2_14_FN, GPSR2_14, |
| 2558 | GP_2_13_FN, GPSR2_13, |
| 2559 | GP_2_12_FN, GPSR2_12, |
| 2560 | GP_2_11_FN, GPSR2_11, |
| 2561 | GP_2_10_FN, GPSR2_10, |
| 2562 | GP_2_9_FN, GPSR2_9, |
| 2563 | GP_2_8_FN, GPSR2_8, |
| 2564 | GP_2_7_FN, GPSR2_7, |
| 2565 | GP_2_6_FN, GPSR2_6, |
| 2566 | GP_2_5_FN, GPSR2_5, |
| 2567 | GP_2_4_FN, GPSR2_4, |
| 2568 | GP_2_3_FN, GPSR2_3, |
| 2569 | GP_2_2_FN, GPSR2_2, |
| 2570 | GP_2_1_FN, GPSR2_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2571 | GP_2_0_FN, GPSR2_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2572 | }, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2573 | { PINMUX_CFG_REG_VAR("GPSR3", 0xe606010c, 32, |
| 2574 | GROUP(-22, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 2575 | GROUP( |
| 2576 | /* GP3_31_10 RESERVED */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2577 | GP_3_9_FN, GPSR3_9, |
| 2578 | GP_3_8_FN, GPSR3_8, |
| 2579 | GP_3_7_FN, GPSR3_7, |
| 2580 | GP_3_6_FN, GPSR3_6, |
| 2581 | GP_3_5_FN, GPSR3_5, |
| 2582 | GP_3_4_FN, GPSR3_4, |
| 2583 | GP_3_3_FN, GPSR3_3, |
| 2584 | GP_3_2_FN, GPSR3_2, |
| 2585 | GP_3_1_FN, GPSR3_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2586 | GP_3_0_FN, GPSR3_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2587 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2588 | { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2589 | GP_4_31_FN, GPSR4_31, |
| 2590 | GP_4_30_FN, GPSR4_30, |
| 2591 | GP_4_29_FN, GPSR4_29, |
| 2592 | GP_4_28_FN, GPSR4_28, |
| 2593 | GP_4_27_FN, GPSR4_27, |
| 2594 | GP_4_26_FN, GPSR4_26, |
| 2595 | GP_4_25_FN, GPSR4_25, |
| 2596 | GP_4_24_FN, GPSR4_24, |
| 2597 | GP_4_23_FN, GPSR4_23, |
| 2598 | GP_4_22_FN, GPSR4_22, |
| 2599 | GP_4_21_FN, GPSR4_21, |
| 2600 | GP_4_20_FN, GPSR4_20, |
| 2601 | GP_4_19_FN, GPSR4_19, |
| 2602 | GP_4_18_FN, GPSR4_18, |
| 2603 | GP_4_17_FN, GPSR4_17, |
| 2604 | GP_4_16_FN, GPSR4_16, |
| 2605 | GP_4_15_FN, GPSR4_15, |
| 2606 | GP_4_14_FN, GPSR4_14, |
| 2607 | GP_4_13_FN, GPSR4_13, |
| 2608 | GP_4_12_FN, GPSR4_12, |
| 2609 | GP_4_11_FN, GPSR4_11, |
| 2610 | GP_4_10_FN, GPSR4_10, |
| 2611 | GP_4_9_FN, GPSR4_9, |
| 2612 | GP_4_8_FN, GPSR4_8, |
| 2613 | GP_4_7_FN, GPSR4_7, |
| 2614 | GP_4_6_FN, GPSR4_6, |
| 2615 | GP_4_5_FN, GPSR4_5, |
| 2616 | GP_4_4_FN, GPSR4_4, |
| 2617 | GP_4_3_FN, GPSR4_3, |
| 2618 | GP_4_2_FN, GPSR4_2, |
| 2619 | GP_4_1_FN, GPSR4_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2620 | GP_4_0_FN, GPSR4_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2621 | }, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2622 | { PINMUX_CFG_REG_VAR("GPSR5", 0xe6060114, 32, |
| 2623 | GROUP(-11, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 2624 | 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), |
| 2625 | GROUP( |
| 2626 | /* GP5_31_21 RESERVED */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2627 | GP_5_20_FN, GPSR5_20, |
| 2628 | GP_5_19_FN, GPSR5_19, |
| 2629 | GP_5_18_FN, GPSR5_18, |
| 2630 | GP_5_17_FN, GPSR5_17, |
| 2631 | GP_5_16_FN, GPSR5_16, |
| 2632 | GP_5_15_FN, GPSR5_15, |
| 2633 | GP_5_14_FN, GPSR5_14, |
| 2634 | GP_5_13_FN, GPSR5_13, |
| 2635 | GP_5_12_FN, GPSR5_12, |
| 2636 | GP_5_11_FN, GPSR5_11, |
| 2637 | GP_5_10_FN, GPSR5_10, |
| 2638 | GP_5_9_FN, GPSR5_9, |
| 2639 | GP_5_8_FN, GPSR5_8, |
| 2640 | GP_5_7_FN, GPSR5_7, |
| 2641 | GP_5_6_FN, GPSR5_6, |
| 2642 | GP_5_5_FN, GPSR5_5, |
| 2643 | GP_5_4_FN, GPSR5_4, |
| 2644 | GP_5_3_FN, GPSR5_3, |
| 2645 | GP_5_2_FN, GPSR5_2, |
| 2646 | GP_5_1_FN, GPSR5_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2647 | GP_5_0_FN, GPSR5_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2648 | }, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2649 | { PINMUX_CFG_REG_VAR("GPSR6", 0xe6060118, 32, |
| 2650 | GROUP(-18, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, |
| 2651 | 1, 1, 1), |
| 2652 | GROUP( |
| 2653 | /* GP6_31_14 RESERVED */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2654 | GP_6_13_FN, GPSR6_13, |
| 2655 | GP_6_12_FN, GPSR6_12, |
| 2656 | GP_6_11_FN, GPSR6_11, |
| 2657 | GP_6_10_FN, GPSR6_10, |
| 2658 | GP_6_9_FN, GPSR6_9, |
| 2659 | GP_6_8_FN, GPSR6_8, |
| 2660 | GP_6_7_FN, GPSR6_7, |
| 2661 | GP_6_6_FN, GPSR6_6, |
| 2662 | GP_6_5_FN, GPSR6_5, |
| 2663 | GP_6_4_FN, GPSR6_4, |
| 2664 | GP_6_3_FN, GPSR6_3, |
| 2665 | GP_6_2_FN, GPSR6_2, |
| 2666 | GP_6_1_FN, GPSR6_1, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2667 | GP_6_0_FN, GPSR6_0, )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2668 | }, |
| 2669 | #undef F_ |
| 2670 | #undef FM |
| 2671 | |
| 2672 | #define F_(x, y) x, |
| 2673 | #define FM(x) FN_##x, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2674 | { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2675 | IP0_31_28 |
| 2676 | IP0_27_24 |
| 2677 | IP0_23_20 |
| 2678 | IP0_19_16 |
| 2679 | IP0_15_12 |
| 2680 | IP0_11_8 |
| 2681 | IP0_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2682 | IP0_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2683 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2684 | { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2685 | IP1_31_28 |
| 2686 | IP1_27_24 |
| 2687 | IP1_23_20 |
| 2688 | IP1_19_16 |
| 2689 | IP1_15_12 |
| 2690 | IP1_11_8 |
| 2691 | IP1_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2692 | IP1_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2693 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2694 | { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2695 | IP2_31_28 |
| 2696 | IP2_27_24 |
| 2697 | IP2_23_20 |
| 2698 | IP2_19_16 |
| 2699 | IP2_15_12 |
| 2700 | IP2_11_8 |
| 2701 | IP2_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2702 | IP2_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2703 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2704 | { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2705 | IP3_31_28 |
| 2706 | IP3_27_24 |
| 2707 | IP3_23_20 |
| 2708 | IP3_19_16 |
| 2709 | IP3_15_12 |
| 2710 | IP3_11_8 |
| 2711 | IP3_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2712 | IP3_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2713 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2714 | { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2715 | IP4_31_28 |
| 2716 | IP4_27_24 |
| 2717 | IP4_23_20 |
| 2718 | IP4_19_16 |
| 2719 | IP4_15_12 |
| 2720 | IP4_11_8 |
| 2721 | IP4_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2722 | IP4_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2723 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2724 | { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2725 | IP5_31_28 |
| 2726 | IP5_27_24 |
| 2727 | IP5_23_20 |
| 2728 | IP5_19_16 |
| 2729 | IP5_15_12 |
| 2730 | IP5_11_8 |
| 2731 | IP5_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2732 | IP5_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2733 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2734 | { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2735 | IP6_31_28 |
| 2736 | IP6_27_24 |
| 2737 | IP6_23_20 |
| 2738 | IP6_19_16 |
| 2739 | IP6_15_12 |
| 2740 | IP6_11_8 |
| 2741 | IP6_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2742 | IP6_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2743 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2744 | { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2745 | IP7_31_28 |
| 2746 | IP7_27_24 |
| 2747 | IP7_23_20 |
| 2748 | IP7_19_16 |
| 2749 | IP7_15_12 |
| 2750 | IP7_11_8 |
| 2751 | IP7_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2752 | IP7_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2753 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2754 | { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2755 | IP8_31_28 |
| 2756 | IP8_27_24 |
| 2757 | IP8_23_20 |
| 2758 | IP8_19_16 |
| 2759 | IP8_15_12 |
| 2760 | IP8_11_8 |
| 2761 | IP8_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2762 | IP8_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2763 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2764 | { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2765 | IP9_31_28 |
| 2766 | IP9_27_24 |
| 2767 | IP9_23_20 |
| 2768 | IP9_19_16 |
| 2769 | IP9_15_12 |
| 2770 | IP9_11_8 |
| 2771 | IP9_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2772 | IP9_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2773 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2774 | { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2775 | IP10_31_28 |
| 2776 | IP10_27_24 |
| 2777 | IP10_23_20 |
| 2778 | IP10_19_16 |
| 2779 | IP10_15_12 |
| 2780 | IP10_11_8 |
| 2781 | IP10_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2782 | IP10_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2783 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2784 | { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2785 | IP11_31_28 |
| 2786 | IP11_27_24 |
| 2787 | IP11_23_20 |
| 2788 | IP11_19_16 |
| 2789 | IP11_15_12 |
| 2790 | IP11_11_8 |
| 2791 | IP11_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2792 | IP11_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2793 | }, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2794 | { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4, GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2795 | IP12_31_28 |
| 2796 | IP12_27_24 |
| 2797 | IP12_23_20 |
| 2798 | IP12_19_16 |
| 2799 | IP12_15_12 |
| 2800 | IP12_11_8 |
| 2801 | IP12_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2802 | IP12_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2803 | }, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2804 | { PINMUX_CFG_REG_VAR("IPSR13", 0xe6060234, 32, |
| 2805 | GROUP(-24, 4, 4), |
| 2806 | GROUP( |
| 2807 | /* IP13_31_8 RESERVED */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2808 | IP13_7_4 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2809 | IP13_3_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2810 | }, |
| 2811 | #undef F_ |
| 2812 | #undef FM |
| 2813 | |
| 2814 | #define F_(x, y) x, |
| 2815 | #define FM(x) FN_##x, |
| 2816 | { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2817 | GROUP(-1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, -1, |
| 2818 | 1, 1, 1, 1, 1, 1, -4, 1, 1, 1, 1, 1, 1), |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2819 | GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2820 | /* RESERVED 31 */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2821 | MOD_SEL0_30 |
| 2822 | MOD_SEL0_29 |
| 2823 | MOD_SEL0_28 |
| 2824 | MOD_SEL0_27 |
| 2825 | MOD_SEL0_26 |
| 2826 | MOD_SEL0_25 |
| 2827 | MOD_SEL0_24_23 |
| 2828 | MOD_SEL0_22_21 |
| 2829 | MOD_SEL0_20_19 |
| 2830 | MOD_SEL0_18_17 |
| 2831 | /* RESERVED 16 */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2832 | MOD_SEL0_15 |
| 2833 | MOD_SEL0_14 |
| 2834 | MOD_SEL0_13 |
| 2835 | MOD_SEL0_12 |
| 2836 | MOD_SEL0_11 |
| 2837 | MOD_SEL0_10 |
| 2838 | /* RESERVED 9, 8, 7, 6 */ |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2839 | MOD_SEL0_5 |
| 2840 | MOD_SEL0_4 |
| 2841 | MOD_SEL0_3 |
| 2842 | MOD_SEL0_2 |
| 2843 | MOD_SEL0_1 |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2844 | MOD_SEL0_0 )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2845 | }, |
| 2846 | { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2847 | GROUP(1, 1, 1, 1, 1, 1, -26), |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 2848 | GROUP( |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2849 | MOD_SEL1_31 |
| 2850 | MOD_SEL1_30 |
| 2851 | MOD_SEL1_29 |
| 2852 | MOD_SEL1_28 |
| 2853 | MOD_SEL1_27 |
| 2854 | MOD_SEL1_26 |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2855 | /* RESERVED 25-0 */ )) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2856 | }, |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 2857 | { /* sentinel */ } |
| 2858 | }; |
| 2859 | |
| 2860 | enum ioctrl_regs { |
| 2861 | POCCTRL0, |
| 2862 | POCCTRL2, |
| 2863 | TDSELCTRL, |
| 2864 | }; |
| 2865 | |
| 2866 | static const struct pinmux_ioctrl_reg pinmux_ioctrl_regs[] = { |
| 2867 | [POCCTRL0] = { 0xe6060380, }, |
| 2868 | [POCCTRL2] = { 0xe6060388, }, |
| 2869 | [TDSELCTRL] = { 0xe60603c0, }, |
| 2870 | { /* sentinel */ } |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2871 | }; |
| 2872 | |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 2873 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2874 | static int r8a77995_pin_to_pocctrl(unsigned int pin, u32 *pocctrl) |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2875 | { |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 2876 | switch (pin) { |
| 2877 | case RCAR_GP_PIN(3, 0) ... RCAR_GP_PIN(3, 9): |
| 2878 | *pocctrl = pinmux_ioctrl_regs[POCCTRL0].reg; |
| 2879 | return 29 - (pin - RCAR_GP_PIN(3, 0)); |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2880 | |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 2881 | case PIN_VDDQ_AVB0: |
| 2882 | *pocctrl = pinmux_ioctrl_regs[POCCTRL2].reg; |
| 2883 | return 0; |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2884 | |
Marek Vasut | f5ba8ca | 2023-09-17 16:08:46 +0200 | [diff] [blame] | 2885 | default: |
| 2886 | return -EINVAL; |
| 2887 | } |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 2888 | } |
| 2889 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 2890 | static const struct pinmux_bias_reg pinmux_bias_regs[] = { |
| 2891 | { PINMUX_BIAS_REG("PUEN0", 0xe6060400, "PUD0", 0xe6060440) { |
| 2892 | [ 0] = RCAR_GP_PIN(1, 9), /* DU_DG1 */ |
| 2893 | [ 1] = RCAR_GP_PIN(1, 8), /* DU_DG0 */ |
| 2894 | [ 2] = RCAR_GP_PIN(1, 7), /* DU_DB7 */ |
| 2895 | [ 3] = RCAR_GP_PIN(1, 6), /* DU_DB6 */ |
| 2896 | [ 4] = RCAR_GP_PIN(1, 5), /* DU_DB5 */ |
| 2897 | [ 5] = RCAR_GP_PIN(1, 4), /* DU_DB4 */ |
| 2898 | [ 6] = RCAR_GP_PIN(1, 3), /* DU_DB3 */ |
| 2899 | [ 7] = RCAR_GP_PIN(1, 2), /* DU_DB2 */ |
| 2900 | [ 8] = RCAR_GP_PIN(1, 1), /* DU_DB1 */ |
| 2901 | [ 9] = RCAR_GP_PIN(1, 0), /* DU_DB0 */ |
| 2902 | [10] = PIN_MLB_REF, /* MLB_REF */ |
| 2903 | [11] = RCAR_GP_PIN(0, 8), /* MLB_SIG */ |
| 2904 | [12] = RCAR_GP_PIN(0, 7), /* MLB_DAT */ |
| 2905 | [13] = RCAR_GP_PIN(0, 6), /* MLB_CLK */ |
| 2906 | [14] = RCAR_GP_PIN(0, 5), /* MSIOF2_RXD */ |
| 2907 | [15] = RCAR_GP_PIN(0, 4), /* MSIOF2_TXD */ |
| 2908 | [16] = RCAR_GP_PIN(0, 3), /* MSIOF2_SCK */ |
| 2909 | [17] = RCAR_GP_PIN(0, 2), /* IRQ0_A */ |
| 2910 | [18] = RCAR_GP_PIN(0, 1), /* USB0_OVC */ |
| 2911 | [19] = RCAR_GP_PIN(0, 0), /* USB0_PWEN */ |
| 2912 | [20] = PIN_PRESETOUT_N, /* PRESETOUT# */ |
| 2913 | [21] = PIN_DU_DOTCLKIN0, /* DU_DOTCLKIN0 */ |
| 2914 | [22] = PIN_FSCLKST_N, /* FSCLKST# */ |
| 2915 | [23] = SH_PFC_PIN_NONE, |
| 2916 | [24] = SH_PFC_PIN_NONE, |
| 2917 | [25] = SH_PFC_PIN_NONE, |
| 2918 | [26] = SH_PFC_PIN_NONE, |
| 2919 | [27] = SH_PFC_PIN_NONE, |
| 2920 | [28] = PIN_TDI, /* TDI */ |
| 2921 | [29] = PIN_TMS, /* TMS */ |
| 2922 | [30] = PIN_TCK, /* TCK */ |
| 2923 | [31] = PIN_TRST_N, /* TRST# */ |
| 2924 | } }, |
| 2925 | { PINMUX_BIAS_REG("PUEN1", 0xe6060404, "PUD1", 0xe6060444) { |
| 2926 | [ 0] = RCAR_GP_PIN(2, 9), /* VI4_DATA8 */ |
| 2927 | [ 1] = RCAR_GP_PIN(2, 8), /* VI4_DATA7 */ |
| 2928 | [ 2] = RCAR_GP_PIN(2, 7), /* VI4_DATA6 */ |
| 2929 | [ 3] = RCAR_GP_PIN(2, 6), /* VI4_DATA5 */ |
| 2930 | [ 4] = RCAR_GP_PIN(2, 5), /* VI4_DATA4 */ |
| 2931 | [ 5] = RCAR_GP_PIN(2, 4), /* VI4_DATA3 */ |
| 2932 | [ 6] = RCAR_GP_PIN(2, 3), /* VI4_DATA2 */ |
| 2933 | [ 7] = RCAR_GP_PIN(2, 2), /* VI4_DATA1 */ |
| 2934 | [ 8] = RCAR_GP_PIN(2, 1), /* VI4_DATA0 */ |
| 2935 | [ 9] = RCAR_GP_PIN(2, 0), /* VI4_CLK */ |
| 2936 | [10] = RCAR_GP_PIN(1, 31), /* QPOLB */ |
| 2937 | [11] = RCAR_GP_PIN(1, 30), /* QPOLA */ |
| 2938 | [12] = RCAR_GP_PIN(1, 29), /* DU_CDE */ |
| 2939 | [13] = RCAR_GP_PIN(1, 28), /* DU_DISP/CDE */ |
| 2940 | [14] = RCAR_GP_PIN(1, 27), /* DU_DISP */ |
| 2941 | [15] = RCAR_GP_PIN(1, 26), /* DU_VSYNC */ |
| 2942 | [16] = RCAR_GP_PIN(1, 25), /* DU_HSYNC */ |
| 2943 | [17] = RCAR_GP_PIN(1, 24), /* DU_DOTCLKOUT0 */ |
| 2944 | [18] = RCAR_GP_PIN(1, 23), /* DU_DR7 */ |
| 2945 | [19] = RCAR_GP_PIN(1, 22), /* DU_DR6 */ |
| 2946 | [20] = RCAR_GP_PIN(1, 21), /* DU_DR5 */ |
| 2947 | [21] = RCAR_GP_PIN(1, 20), /* DU_DR4 */ |
| 2948 | [22] = RCAR_GP_PIN(1, 19), /* DU_DR3 */ |
| 2949 | [23] = RCAR_GP_PIN(1, 18), /* DU_DR2 */ |
| 2950 | [24] = RCAR_GP_PIN(1, 17), /* DU_DR1 */ |
| 2951 | [25] = RCAR_GP_PIN(1, 16), /* DU_DR0 */ |
| 2952 | [26] = RCAR_GP_PIN(1, 15), /* DU_DG7 */ |
| 2953 | [27] = RCAR_GP_PIN(1, 14), /* DU_DG6 */ |
| 2954 | [28] = RCAR_GP_PIN(1, 13), /* DU_DG5 */ |
| 2955 | [29] = RCAR_GP_PIN(1, 12), /* DU_DG4 */ |
| 2956 | [30] = RCAR_GP_PIN(1, 11), /* DU_DG3 */ |
| 2957 | [31] = RCAR_GP_PIN(1, 10), /* DU_DG2 */ |
| 2958 | } }, |
| 2959 | { PINMUX_BIAS_REG("PUEN2", 0xe6060408, "PUD2", 0xe6060448) { |
| 2960 | [ 0] = RCAR_GP_PIN(3, 8), /* NFDATA6 */ |
| 2961 | [ 1] = RCAR_GP_PIN(3, 7), /* NFDATA5 */ |
| 2962 | [ 2] = RCAR_GP_PIN(3, 6), /* NFDATA4 */ |
| 2963 | [ 3] = RCAR_GP_PIN(3, 5), /* NFDATA3 */ |
| 2964 | [ 4] = RCAR_GP_PIN(3, 4), /* NFDATA2 */ |
| 2965 | [ 5] = RCAR_GP_PIN(3, 3), /* NFDATA1 */ |
| 2966 | [ 6] = RCAR_GP_PIN(3, 2), /* NFDATA0 */ |
| 2967 | [ 7] = RCAR_GP_PIN(3, 1), /* NFWE# (PUEN) / NFRE# (PUD) */ |
| 2968 | [ 8] = RCAR_GP_PIN(3, 0), /* NFRE# (PUEN) / NFWE# (PUD) */ |
| 2969 | [ 9] = RCAR_GP_PIN(4, 0), /* NFRB# */ |
| 2970 | [10] = RCAR_GP_PIN(2, 31), /* NFCE# */ |
| 2971 | [11] = RCAR_GP_PIN(2, 30), /* NFCLE */ |
| 2972 | [12] = RCAR_GP_PIN(2, 29), /* NFALE */ |
| 2973 | [13] = RCAR_GP_PIN(2, 28), /* VI4_CLKENB */ |
| 2974 | [14] = RCAR_GP_PIN(2, 27), /* VI4_FIELD */ |
| 2975 | [15] = RCAR_GP_PIN(2, 26), /* VI4_HSYNC# */ |
| 2976 | [16] = RCAR_GP_PIN(2, 25), /* VI4_VSYNC# */ |
| 2977 | [17] = RCAR_GP_PIN(2, 24), /* VI4_DATA23 */ |
| 2978 | [18] = RCAR_GP_PIN(2, 23), /* VI4_DATA22 */ |
| 2979 | [19] = RCAR_GP_PIN(2, 22), /* VI4_DATA21 */ |
| 2980 | [20] = RCAR_GP_PIN(2, 21), /* VI4_DATA20 */ |
| 2981 | [21] = RCAR_GP_PIN(2, 20), /* VI4_DATA19 */ |
| 2982 | [22] = RCAR_GP_PIN(2, 19), /* VI4_DATA18 */ |
| 2983 | [23] = RCAR_GP_PIN(2, 18), /* VI4_DATA17 */ |
| 2984 | [24] = RCAR_GP_PIN(2, 17), /* VI4_DATA16 */ |
| 2985 | [25] = RCAR_GP_PIN(2, 16), /* VI4_DATA15 */ |
| 2986 | [26] = RCAR_GP_PIN(2, 15), /* VI4_DATA14 */ |
| 2987 | [27] = RCAR_GP_PIN(2, 14), /* VI4_DATA13 */ |
| 2988 | [28] = RCAR_GP_PIN(2, 13), /* VI4_DATA12 */ |
| 2989 | [29] = RCAR_GP_PIN(2, 12), /* VI4_DATA11 */ |
| 2990 | [30] = RCAR_GP_PIN(2, 11), /* VI4_DATA10 */ |
| 2991 | [31] = RCAR_GP_PIN(2, 10), /* VI4_DATA9 */ |
| 2992 | } }, |
| 2993 | { PINMUX_BIAS_REG("PUEN3", 0xe606040c, "PUD3", 0xe606044c) { |
| 2994 | [ 0] = RCAR_GP_PIN(4, 31), /* CAN0_RX_A */ |
| 2995 | [ 1] = RCAR_GP_PIN(5, 2), /* CAN_CLK */ |
| 2996 | [ 2] = RCAR_GP_PIN(5, 1), /* TPU0TO1_A */ |
| 2997 | [ 3] = RCAR_GP_PIN(5, 0), /* TPU0TO0_A */ |
| 2998 | [ 4] = RCAR_GP_PIN(4, 27), /* TX2 */ |
| 2999 | [ 5] = RCAR_GP_PIN(4, 26), /* RX2 */ |
| 3000 | [ 6] = RCAR_GP_PIN(4, 25), /* SCK2 */ |
| 3001 | [ 7] = RCAR_GP_PIN(4, 24), /* TX1_A */ |
| 3002 | [ 8] = RCAR_GP_PIN(4, 23), /* RX1_A */ |
| 3003 | [ 9] = RCAR_GP_PIN(4, 22), /* SCK1_A */ |
| 3004 | [10] = RCAR_GP_PIN(4, 21), /* TX0_A */ |
| 3005 | [11] = RCAR_GP_PIN(4, 20), /* RX0_A */ |
| 3006 | [12] = RCAR_GP_PIN(4, 19), /* SCK0_A */ |
| 3007 | [13] = RCAR_GP_PIN(4, 18), /* MSIOF1_RXD */ |
| 3008 | [14] = RCAR_GP_PIN(4, 17), /* MSIOF1_TXD */ |
| 3009 | [15] = RCAR_GP_PIN(4, 16), /* MSIOF1_SCK */ |
| 3010 | [16] = RCAR_GP_PIN(4, 15), /* MSIOF0_RXD */ |
| 3011 | [17] = RCAR_GP_PIN(4, 14), /* MSIOF0_TXD */ |
| 3012 | [18] = RCAR_GP_PIN(4, 13), /* MSIOF0_SYNC */ |
| 3013 | [19] = RCAR_GP_PIN(4, 12), /* MSIOF0_SCK */ |
| 3014 | [20] = RCAR_GP_PIN(4, 11), /* SDA1 */ |
| 3015 | [21] = RCAR_GP_PIN(4, 10), /* SCL1 */ |
| 3016 | [22] = RCAR_GP_PIN(4, 9), /* SDA0 */ |
| 3017 | [23] = RCAR_GP_PIN(4, 8), /* SCL0 */ |
| 3018 | [24] = RCAR_GP_PIN(4, 7), /* SSI_WS4_A */ |
| 3019 | [25] = RCAR_GP_PIN(4, 6), /* SSI_SDATA4_A */ |
| 3020 | [26] = RCAR_GP_PIN(4, 5), /* SSI_SCK4_A */ |
| 3021 | [27] = RCAR_GP_PIN(4, 4), /* SSI_WS34 */ |
| 3022 | [28] = RCAR_GP_PIN(4, 3), /* SSI_SDATA3 */ |
| 3023 | [29] = RCAR_GP_PIN(4, 2), /* SSI_SCK34 */ |
| 3024 | [30] = RCAR_GP_PIN(4, 1), /* AUDIO_CLKA */ |
| 3025 | [31] = RCAR_GP_PIN(3, 9), /* NFDATA7 */ |
| 3026 | } }, |
| 3027 | { PINMUX_BIAS_REG("PUEN4", 0xe6060410, "PUD4", 0xe6060450) { |
| 3028 | [ 0] = RCAR_GP_PIN(6, 10), /* QSPI1_IO3 */ |
| 3029 | [ 1] = RCAR_GP_PIN(6, 9), /* QSPI1_IO2 */ |
| 3030 | [ 2] = RCAR_GP_PIN(6, 8), /* QSPI1_MISO_IO1 */ |
| 3031 | [ 3] = RCAR_GP_PIN(6, 7), /* QSPI1_MOSI_IO0 */ |
| 3032 | [ 4] = RCAR_GP_PIN(6, 6), /* QSPI1_SPCLK */ |
| 3033 | [ 5] = RCAR_GP_PIN(6, 5), /* QSPI0_SSL */ |
| 3034 | [ 6] = RCAR_GP_PIN(6, 4), /* QSPI0_IO3 */ |
| 3035 | [ 7] = RCAR_GP_PIN(6, 3), /* QSPI0_IO2 */ |
| 3036 | [ 8] = RCAR_GP_PIN(6, 2), /* QSPI0_MISO_IO1 */ |
| 3037 | [ 9] = RCAR_GP_PIN(6, 1), /* QSPI0_MOSI_IO0 */ |
| 3038 | [10] = RCAR_GP_PIN(6, 0), /* QSPI0_SPCLK */ |
| 3039 | [11] = RCAR_GP_PIN(5, 20), /* AVB0_LINK */ |
| 3040 | [12] = RCAR_GP_PIN(5, 19), /* AVB0_PHY_INT */ |
| 3041 | [13] = RCAR_GP_PIN(5, 18), /* AVB0_MAGIC */ |
| 3042 | [14] = RCAR_GP_PIN(5, 17), /* AVB0_MDC */ |
| 3043 | [15] = RCAR_GP_PIN(5, 16), /* AVB0_MDIO */ |
| 3044 | [16] = RCAR_GP_PIN(5, 15), /* AVB0_TXCREFCLK */ |
| 3045 | [17] = RCAR_GP_PIN(5, 14), /* AVB0_TD3 */ |
| 3046 | [18] = RCAR_GP_PIN(5, 13), /* AVB0_TD2 */ |
| 3047 | [19] = RCAR_GP_PIN(5, 12), /* AVB0_TD1 */ |
| 3048 | [20] = RCAR_GP_PIN(5, 11), /* AVB0_TD0 */ |
| 3049 | [21] = RCAR_GP_PIN(5, 10), /* AVB0_TXC */ |
| 3050 | [22] = RCAR_GP_PIN(5, 9), /* AVB0_TX_CTL */ |
| 3051 | [23] = RCAR_GP_PIN(5, 8), /* AVB0_RD3 */ |
| 3052 | [24] = RCAR_GP_PIN(5, 7), /* AVB0_RD2 */ |
| 3053 | [25] = RCAR_GP_PIN(5, 6), /* AVB0_RD1 */ |
| 3054 | [26] = RCAR_GP_PIN(5, 5), /* AVB0_RD0 */ |
| 3055 | [27] = RCAR_GP_PIN(5, 4), /* AVB0_RXC */ |
| 3056 | [28] = RCAR_GP_PIN(5, 3), /* AVB0_RX_CTL */ |
| 3057 | [29] = RCAR_GP_PIN(4, 30), /* CAN1_TX_A */ |
| 3058 | [30] = RCAR_GP_PIN(4, 29), /* CAN1_RX_A */ |
| 3059 | [31] = RCAR_GP_PIN(4, 28), /* CAN0_TX_A */ |
| 3060 | } }, |
| 3061 | { PINMUX_BIAS_REG("PUEN5", 0xe6060414, "PUD4", 0xe6060454) { |
| 3062 | [ 0] = SH_PFC_PIN_NONE, |
| 3063 | [ 1] = SH_PFC_PIN_NONE, |
| 3064 | [ 2] = SH_PFC_PIN_NONE, |
| 3065 | [ 3] = SH_PFC_PIN_NONE, |
| 3066 | [ 4] = SH_PFC_PIN_NONE, |
| 3067 | [ 5] = SH_PFC_PIN_NONE, |
| 3068 | [ 6] = SH_PFC_PIN_NONE, |
| 3069 | [ 7] = SH_PFC_PIN_NONE, |
| 3070 | [ 8] = SH_PFC_PIN_NONE, |
| 3071 | [ 9] = SH_PFC_PIN_NONE, |
| 3072 | [10] = SH_PFC_PIN_NONE, |
| 3073 | [11] = SH_PFC_PIN_NONE, |
| 3074 | [12] = SH_PFC_PIN_NONE, |
| 3075 | [13] = SH_PFC_PIN_NONE, |
| 3076 | [14] = SH_PFC_PIN_NONE, |
| 3077 | [15] = SH_PFC_PIN_NONE, |
| 3078 | [16] = SH_PFC_PIN_NONE, |
| 3079 | [17] = SH_PFC_PIN_NONE, |
| 3080 | [18] = SH_PFC_PIN_NONE, |
| 3081 | [19] = SH_PFC_PIN_NONE, |
| 3082 | [20] = SH_PFC_PIN_NONE, |
| 3083 | [21] = SH_PFC_PIN_NONE, |
| 3084 | [22] = SH_PFC_PIN_NONE, |
| 3085 | [23] = SH_PFC_PIN_NONE, |
| 3086 | [24] = SH_PFC_PIN_NONE, |
| 3087 | [25] = SH_PFC_PIN_NONE, |
| 3088 | [26] = SH_PFC_PIN_NONE, |
| 3089 | [27] = SH_PFC_PIN_NONE, |
| 3090 | [28] = SH_PFC_PIN_NONE, |
| 3091 | [29] = RCAR_GP_PIN(6, 13), /* RPC_INT# */ |
| 3092 | [30] = RCAR_GP_PIN(6, 12), /* RPC_RESET# */ |
| 3093 | [31] = RCAR_GP_PIN(6, 11), /* QSPI1_SSL */ |
| 3094 | } }, |
| 3095 | { /* sentinel */ } |
| 3096 | }; |
| 3097 | |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 3098 | static const struct pinmux_bias_reg * |
| 3099 | r8a77995_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin, |
| 3100 | unsigned int *puen_bit, unsigned int *pud_bit) |
| 3101 | { |
| 3102 | const struct pinmux_bias_reg *reg; |
| 3103 | unsigned int bit; |
| 3104 | |
| 3105 | reg = rcar_pin_to_bias_reg(pfc->info, pin, &bit); |
| 3106 | if (!reg) |
| 3107 | return reg; |
| 3108 | |
| 3109 | *puen_bit = bit; |
| 3110 | |
| 3111 | /* NFWE# and NFRE# use different bit positions in PUD2 */ |
| 3112 | switch (pin) { |
| 3113 | case RCAR_GP_PIN(3, 0): /* NFRE# */ |
| 3114 | *pud_bit = 7; |
| 3115 | break; |
| 3116 | |
| 3117 | case RCAR_GP_PIN(3, 1): /* NFWE# */ |
| 3118 | *pud_bit = 8; |
| 3119 | break; |
| 3120 | |
| 3121 | default: |
| 3122 | *pud_bit = bit; |
| 3123 | break; |
| 3124 | } |
| 3125 | |
| 3126 | return reg; |
| 3127 | } |
| 3128 | |
| 3129 | static unsigned int r8a77995_pinmux_get_bias(struct sh_pfc *pfc, |
| 3130 | unsigned int pin) |
| 3131 | { |
| 3132 | const struct pinmux_bias_reg *reg; |
| 3133 | unsigned int puen_bit, pud_bit; |
| 3134 | |
| 3135 | reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit); |
| 3136 | if (!reg) |
| 3137 | return PIN_CONFIG_BIAS_DISABLE; |
| 3138 | |
| 3139 | if (!(sh_pfc_read(pfc, reg->puen) & BIT(puen_bit))) |
| 3140 | return PIN_CONFIG_BIAS_DISABLE; |
| 3141 | else if (sh_pfc_read(pfc, reg->pud) & BIT(pud_bit)) |
| 3142 | return PIN_CONFIG_BIAS_PULL_UP; |
| 3143 | else |
| 3144 | return PIN_CONFIG_BIAS_PULL_DOWN; |
| 3145 | } |
| 3146 | |
| 3147 | static void r8a77995_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, |
| 3148 | unsigned int bias) |
| 3149 | { |
| 3150 | const struct pinmux_bias_reg *reg; |
| 3151 | unsigned int puen_bit, pud_bit; |
| 3152 | u32 enable, updown; |
| 3153 | |
| 3154 | reg = r8a77995_pin_to_bias_reg(pfc, pin, &puen_bit, &pud_bit); |
| 3155 | if (!reg) |
| 3156 | return; |
| 3157 | |
| 3158 | enable = sh_pfc_read(pfc, reg->puen) & ~BIT(puen_bit); |
| 3159 | if (bias != PIN_CONFIG_BIAS_DISABLE) { |
| 3160 | enable |= BIT(puen_bit); |
| 3161 | |
| 3162 | updown = sh_pfc_read(pfc, reg->pud) & ~BIT(pud_bit); |
| 3163 | if (bias == PIN_CONFIG_BIAS_PULL_UP) |
| 3164 | updown |= BIT(pud_bit); |
| 3165 | |
| 3166 | sh_pfc_write(pfc, reg->pud, updown); |
| 3167 | } |
| 3168 | sh_pfc_write(pfc, reg->puen, enable); |
| 3169 | } |
| 3170 | |
| 3171 | static const struct sh_pfc_soc_operations r8a77995_pfc_ops = { |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 3172 | .pin_to_pocctrl = r8a77995_pin_to_pocctrl, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 3173 | .get_bias = r8a77995_pinmux_get_bias, |
| 3174 | .set_bias = r8a77995_pinmux_set_bias, |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 3175 | }; |
| 3176 | |
| 3177 | const struct sh_pfc_soc_info r8a77995_pinmux_info = { |
| 3178 | .name = "r8a77995_pfc", |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 3179 | .ops = &r8a77995_pfc_ops, |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 3180 | .unlock_reg = 0xe6060000, /* PMMR */ |
| 3181 | |
| 3182 | .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, |
| 3183 | |
| 3184 | .pins = pinmux_pins, |
| 3185 | .nr_pins = ARRAY_SIZE(pinmux_pins), |
| 3186 | .groups = pinmux_groups, |
| 3187 | .nr_groups = ARRAY_SIZE(pinmux_groups), |
| 3188 | .functions = pinmux_functions, |
| 3189 | .nr_functions = ARRAY_SIZE(pinmux_functions), |
| 3190 | |
| 3191 | .cfg_regs = pinmux_config_regs, |
Marek Vasut | b8f6113 | 2023-01-26 21:01:46 +0100 | [diff] [blame] | 3192 | .bias_regs = pinmux_bias_regs, |
Eugeniu Rosca | f0066b0 | 2019-07-09 18:27:11 +0200 | [diff] [blame] | 3193 | .ioctrl_regs = pinmux_ioctrl_regs, |
Marek Vasut | 7d35e64 | 2017-10-08 20:57:37 +0200 | [diff] [blame] | 3194 | |
| 3195 | .pinmux_data = pinmux_data, |
| 3196 | .pinmux_data_size = ARRAY_SIZE(pinmux_data), |
| 3197 | }; |