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git01.mediatek.com / filogic / uboot / 15bc1ca85d1d5952a21fb762b501373dfe50f629 / . / arch / arm / dts / k3-am654-base-board-u-boot.dtsi
blob: b0602d1dad2bca3b5a80df1c57549ee1ff9a9071 [file] [log] [blame]
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
Andreas Dannenbergbfdf4982019-04-29 12:56:44 -0500[diff] [blame]6#include <dt-bindings/pinctrl/k3.h>
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]7#include <dt-bindings/net/ti-dp83867.h>
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]8
9/ {
10 chosen {
11 stdout-path = "serial2:115200n8";
12 };
13
14 aliases {
15 serial2 = &main_uart0;
Grygorii Strashkob33dd702019-07-09 10:30:35 +0530[diff] [blame]16 ethernet0 = &cpsw_port1;
Aswath Govindrajudfe082e2020-11-20 21:18:55 +0530[diff] [blame]17 usb0 = &usb0;
18 usb1 = &usb1;
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]19 spi0 = &ospi0;
20 spi1 = &ospi1;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]21 };
22};
23
24&cbass_main{
25 u-boot,dm-spl;
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]26 main-navss {
27 u-boot,dm-spl;
28 };
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]29};
30
31&cbass_mcu {
32 u-boot,dm-spl;
Grygorii Strashko2d457302019-02-05 17:31:26 +0530[diff] [blame]33
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]34 mcu-navss {
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]35 u-boot,dm-spl;
Grygorii Strashko2d457302019-02-05 17:31:26 +0530[diff] [blame]36
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame]37 ringacc@2b800000 {
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]38 u-boot,dm-spl;
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]39 ti,dma-ring-reset-quirk;
Grygorii Strashko2d457302019-02-05 17:31:26 +0530[diff] [blame]40 };
41
Vignesh Raghavendra01250d82020-07-07 13:43:35 +0530[diff] [blame]42 dma-controller@285c0000 {
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]43 u-boot,dm-spl;
Grygorii Strashko2d457302019-02-05 17:31:26 +0530[diff] [blame]44 };
45 };
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]46};
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]47
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]48&cbass_wakeup {
49 u-boot,dm-spl;
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]50
51 chipid@43000014 {
52 u-boot,dm-spl;
53 };
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]54};
55
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]56&secure_proxy_main {
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]57 u-boot,dm-spl;
58};
59
60&dmsc {
61 u-boot,dm-spl;
Lokesh Vutla3d09ed32018-11-02 19:51:08 +0530[diff] [blame]62 k3_sysreset: sysreset-controller {
63 compatible = "ti,sci-sysreset";
64 u-boot,dm-spl;
65 };
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]66};
67
68&k3_pds {
69 u-boot,dm-spl;
70};
71
72&k3_clks {
73 u-boot,dm-spl;
74};
75
76&k3_reset {
77 u-boot,dm-spl;
78};
79
Andreas Dannenbergd20cf7b2019-06-04 18:08:15 -0500[diff] [blame]80&wkup_pmx0 {
81 u-boot,dm-spl;
82
83 wkup_i2c0_pins_default {
84 u-boot,dm-spl;
85 };
86};
87
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]88&main_pmx0 {
89 u-boot,dm-spl;
Faiz Abbas07383712020-08-03 11:35:12 +0530[diff] [blame]90 usb0_pins_default: usb0_pins_default {
91 pinctrl-single,pins = <
92 AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */
93 >;
94 u-boot,dm-spl;
95 };
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]96};
97
Lokesh Vutla462275c2021-02-01 11:26:39 +0530[diff] [blame]98&main_uart0_pins_default {
99 u-boot,dm-spl;
100};
101
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]102&main_pmx1 {
103 u-boot,dm-spl;
104};
105
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]106&wkup_pmx0 {
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]107 mcu-fss0-ospi0-pins-default {
108 u-boot,dm-spl;
109 };
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]110};
111
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]112&main_uart0 {
113 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]114};
115
Faiz Abbas43f69202021-02-04 15:10:56 +0530[diff] [blame]116&main_mmc0_pins_default {
117 u-boot,dm-spl;
118};
119
120&main_mmc1_pins_default {
121 u-boot,dm-spl;
122};
123
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]124&sdhci0 {
125 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]126};
127
128&sdhci1 {
129 u-boot,dm-spl;
Lokesh Vutla76a36492018-08-27 15:59:09 +0530[diff] [blame]130};
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]131
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]132&davinci_mdio {
133 phy0: ethernet-phy@0 {
134 reg = <0>;
135 /* TODO: phy reset: TCA9555RTWR(i2c:0x21)[p04].GPIO_MCU_RGMII_RSTN */
136 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]137 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
138 };
139};
140
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]141&mcu_cpsw {
142 reg = <0x0 0x46000000 0x0 0x200000>,
143 <0x0 0x40f00200 0x0 0x2>;
144 reg-names = "cpsw_nuss", "mac_efuse";
Vignesh Raghavendra388b1172020-07-06 13:36:56 +0530[diff] [blame]145 /delete-property/ ranges;
Grygorii Strashko08512392019-07-09 10:30:36 +0530[diff] [blame]146
147 cpsw-phy-sel@40f04040 {
148 compatible = "ti,am654-cpsw-phy-sel";
149 reg= <0x0 0x40f04040 0x0 0x4>;
150 reg-names = "gmii-sel";
151 };
152};
Andreas Dannenbergd20cf7b2019-06-04 18:08:15 -0500[diff] [blame]153
154&wkup_i2c0 {
155 u-boot,dm-spl;
156};
Vignesh Raghavendra5bbcabb2019-12-09 10:37:33 +0530[diff] [blame]157
158&usb1 {
159 dr_mode = "peripheral";
160};
Vignesh Raghavendra1ee79552020-02-04 11:09:51 +0530[diff] [blame]161
162&fss {
163 u-boot,dm-spl;
164};
165
166&ospi0 {
167 u-boot,dm-spl;
168
169 flash@0{
170 u-boot,dm-spl;
171 };
172};
Dave Gerlachc70c4962020-07-15 23:40:00 -0500[diff] [blame]173
Faiz Abbas07383712020-08-03 11:35:12 +0530[diff] [blame]174&dwc3_0 {
175 status = "okay";
176 u-boot,dm-spl;
177};
178
179&usb0_phy {
180 status = "okay";
181 u-boot,dm-spl;
182};
183
184&usb0 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&usb0_pins_default>;
Aswath Govindraju44623c42020-11-20 21:18:54 +0530[diff] [blame]187 dr_mode = "host";
Faiz Abbas07383712020-08-03 11:35:12 +0530[diff] [blame]188 u-boot,dm-spl;
189};
190
191&scm_conf {
192 u-boot,dm-spl;
193};