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git01.mediatek.com / filogic / uboot / 15a30c2c75f95b90aed9bc0eb77f5d09489c118f / . / arch / arm / dts / rk3308.dtsi
blob: 0eeec165d4d4a6e50d84fb7af86c7b5d577860a4 [file] [log] [blame]
Andy Yan02133dd2019-11-14 11:21:14 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+ OR MIT
2/*
3 * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd
4 *
5 */
6
7#include <dt-bindings/clock/rk3308-cru.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/interrupt-controller/arm-gic.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/pinctrl/rockchip.h>
12#include <dt-bindings/thermal/thermal.h>
13
14/ {
15 compatible = "rockchip,rk3308";
16
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 aliases {
22 i2c0 = &i2c0;
23 i2c1 = &i2c1;
24 i2c2 = &i2c2;
25 i2c3 = &i2c3;
26 serial0 = &uart0;
27 serial1 = &uart1;
28 serial2 = &uart2;
29 serial3 = &uart3;
30 serial4 = &uart4;
31 spi0 = &spi0;
32 spi1 = &spi1;
33 spi2 = &spi2;
34 };
35
36 cpus {
37 #address-cells = <2>;
38 #size-cells = <0>;
39
40 cpu0: cpu@0 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a35", "arm,armv8";
43 reg = <0x0 0x0>;
44 enable-method = "psci";
45 clocks = <&cru ARMCLK>;
46 #cooling-cells = <2>;
47 dynamic-power-coefficient = <90>;
48 operating-points-v2 = <&cpu0_opp_table>;
49 cpu-idle-states = <&CPU_SLEEP>;
50 next-level-cache = <&l2>;
51 };
52
53 cpu1: cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a35", "arm,armv8";
56 reg = <0x0 0x1>;
57 enable-method = "psci";
58 operating-points-v2 = <&cpu0_opp_table>;
59 cpu-idle-states = <&CPU_SLEEP>;
60 next-level-cache = <&l2>;
61 };
62
63 cpu2: cpu@2 {
64 device_type = "cpu";
65 compatible = "arm,cortex-a35", "arm,armv8";
66 reg = <0x0 0x2>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 cpu-idle-states = <&CPU_SLEEP>;
70 next-level-cache = <&l2>;
71 };
72
73 cpu3: cpu@3 {
74 device_type = "cpu";
75 compatible = "arm,cortex-a35", "arm,armv8";
76 reg = <0x0 0x3>;
77 enable-method = "psci";
78 operating-points-v2 = <&cpu0_opp_table>;
79 cpu-idle-states = <&CPU_SLEEP>;
80 next-level-cache = <&l2>;
81 };
82
83 idle-states {
84 entry-method = "psci";
85
86 CPU_SLEEP: cpu-sleep {
87 compatible = "arm,idle-state";
88 local-timer-stop;
89 arm,psci-suspend-param = <0x0010000>;
90 entry-latency-us = <120>;
91 exit-latency-us = <250>;
92 min-residency-us = <900>;
93 };
94 };
95
96 l2: l2-cache {
97 compatible = "cache";
98 };
99 };
100
101 cpu0_opp_table: cpu0-opp-table {
102 compatible = "operating-points-v2";
103 opp-shared;
104
105 opp-408000000 {
106 opp-hz = /bits/ 64 <408000000>;
107 opp-microvolt = <950000 950000 1340000>;
108 clock-latency-ns = <40000>;
109 opp-suspend;
110 };
111 opp-600000000 {
112 opp-hz = /bits/ 64 <600000000>;
113 opp-microvolt = <950000 950000 1340000>;
114 clock-latency-ns = <40000>;
115 };
116 opp-816000000 {
117 opp-hz = /bits/ 64 <816000000>;
118 opp-microvolt = <1025000 1025000 1340000>;
119 clock-latency-ns = <40000>;
120 };
121 opp-1008000000 {
122 opp-hz = /bits/ 64 <1008000000>;
123 opp-microvolt = <1125000 1125000 1340000>;
124 clock-latency-ns = <40000>;
125 };
126 };
127
128 arm-pmu {
129 compatible = "arm,cortex-a53-pmu";
130 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
133 <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
134 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
135 };
136
137 mac_clkin: external-mac-clock {
138 compatible = "fixed-clock";
139 clock-frequency = <50000000>;
140 clock-output-names = "mac_clkin";
141 #clock-cells = <0>;
142 };
143
144 psci {
145 compatible = "arm,psci-1.0";
146 method = "smc";
147 };
148
149 timer {
150 compatible = "arm,armv8-timer";
151 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
152 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
153 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
154 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
155 };
156
157 xin24m: xin24m {
158 compatible = "fixed-clock";
159 #clock-cells = <0>;
160 clock-frequency = <24000000>;
161 clock-output-names = "xin24m";
162 };
163
164 grf: grf@ff000000 {
165 compatible = "rockchip,rk3308-grf", "syscon", "simple-mfd";
166 reg = <0x0 0xff000000 0x0 0x10000>;
167 };
168
169 dmc: dmc@0xff010000 {
170 compatible = "rockchip,rk3308-dmc";
171 reg = <0x0 0xff010000 0x0 0x10000>;
172 };
173
174 detect_grf: syscon@ff00b000 {
175 compatible = "rockchip,rk3308-detect-grf", "syscon", "simple-mfd";
176 reg = <0x0 0xff00b000 0x0 0x1000>;
177 #address-cells = <1>;
178 #size-cells = <1>;
179 };
180
181 core_grf: syscon@ff00c000 {
182 compatible = "rockchip,rk3308-core-grf", "syscon", "simple-mfd";
183 reg = <0x0 0xff00c000 0x0 0x1000>;
184 #address-cells = <1>;
185 #size-cells = <1>;
186
187 };
188
189 i2c0: i2c@ff040000 {
190 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
191 reg = <0x0 0xff040000 0x0 0x1000>;
192 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
193 clock-names = "i2c", "pclk";
194 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
195 pinctrl-names = "default";
196 pinctrl-0 = <&i2c0_xfer>;
197 #address-cells = <1>;
198 #size-cells = <0>;
199 status = "disabled";
200 };
201
202 i2c1: i2c@ff050000 {
203 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
204 reg = <0x0 0xff050000 0x0 0x1000>;
205 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
206 clock-names = "i2c", "pclk";
207 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c1_xfer>;
210 #address-cells = <1>;
211 #size-cells = <0>;
212 status = "disabled";
213 };
214
215 i2c2: i2c@ff060000 {
216 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
217 reg = <0x0 0xff060000 0x0 0x1000>;
218 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
219 clock-names = "i2c", "pclk";
220 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
221 pinctrl-names = "default";
222 pinctrl-0 = <&i2c2_xfer>;
223 #address-cells = <1>;
224 #size-cells = <0>;
225 status = "disabled";
226 };
227
228 i2c3: i2c@ff070000 {
229 compatible = "rockchip,rk3308-i2c", "rockchip,rk3399-i2c";
230 reg = <0x0 0xff070000 0x0 0x1000>;
231 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
232 clock-names = "i2c", "pclk";
233 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
234 pinctrl-names = "default";
235 pinctrl-0 = <&i2c3m0_xfer>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 status = "disabled";
239 };
240
241 wdt: watchdog@ff080000 {
242 compatible = "snps,dw-wdt";
243 reg = <0x0 0xff080000 0x0 0x100>;
244 clocks = <&cru PCLK_WDT>;
245 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
246 status = "disabled";
247 };
248
249 uart0: serial@ff0a0000 {
250 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
251 reg = <0x0 0xff0a0000 0x0 0x100>;
252 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
254 clock-names = "baudclk", "apb_pclk";
255 reg-shift = <2>;
256 reg-io-width = <4>;
257 pinctrl-names = "default";
258 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
259 status = "disabled";
260 };
261
262 uart1: serial@ff0b0000 {
263 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
264 reg = <0x0 0xff0b0000 0x0 0x100>;
265 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
266 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
267 clock-names = "baudclk", "apb_pclk";
268 reg-shift = <2>;
269 reg-io-width = <4>;
270 pinctrl-names = "default";
271 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
272 status = "disabled";
273 };
274
275 uart2: serial@ff0c0000 {
276 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
277 reg = <0x0 0xff0c0000 0x0 0x100>;
278 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
280 clock-names = "baudclk", "apb_pclk";
281 reg-shift = <2>;
282 reg-io-width = <4>;
283 pinctrl-names = "default";
284 pinctrl-0 = <&uart2m0_xfer>;
285 status = "disabled";
286 };
287
288 uart3: serial@ff0d0000 {
289 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
290 reg = <0x0 0xff0d0000 0x0 0x100>;
291 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
293 clock-names = "baudclk", "apb_pclk";
294 reg-shift = <2>;
295 reg-io-width = <4>;
296 pinctrl-names = "default";
297 pinctrl-0 = <&uart3_xfer>;
298 status = "disabled";
299 };
300
301 uart4: serial@ff0e0000 {
302 compatible = "rockchip,rk3308-uart", "snps,dw-apb-uart";
303 reg = <0x0 0xff0e0000 0x0 0x100>;
304 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
306 clock-names = "baudclk", "apb_pclk";
307 reg-shift = <2>;
308 reg-io-width = <4>;
309 pinctrl-names = "default";
310 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>;
311 status = "disabled";
312 };
313
314 spi0: spi@ff120000 {
315 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
316 reg = <0x0 0xff120000 0x0 0x1000>;
317 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
318 #address-cells = <1>;
319 #size-cells = <0>;
320 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
321 clock-names = "spiclk", "apb_pclk";
322 dmas = <&dmac0 0>, <&dmac0 1>;
323 dma-names = "tx", "rx";
324 pinctrl-names = "default", "high_speed";
325 pinctrl-0 = <&spi0_clk &spi0_csn0 &spi0_miso &spi0_mosi>;
326 pinctrl-1 = <&spi0_clk_hs &spi0_csn0 &spi0_miso_hs &spi0_mosi_hs>;
327 status = "disabled";
328 };
329
330 spi1: spi@ff130000 {
331 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
332 reg = <0x0 0xff130000 0x0 0x1000>;
333 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
334 #address-cells = <1>;
335 #size-cells = <0>;
336 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
337 clock-names = "spiclk", "apb_pclk";
338 dmas = <&dmac0 2>, <&dmac0 3>;
339 dma-names = "tx", "rx";
340 pinctrl-names = "default", "high_speed";
341 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_miso &spi1_mosi>;
342 pinctrl-1 = <&spi1_clk_hs &spi1_csn0 &spi1_miso_hs &spi1_mosi_hs>;
343 status = "disabled";
344 };
345
346 spi2: spi@ff140000 {
347 compatible = "rockchip,rk3308-spi", "rockchip,rk3066-spi";
348 reg = <0x0 0xff140000 0x0 0x1000>;
349 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
350 #address-cells = <1>;
351 #size-cells = <0>;
352 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
353 clock-names = "spiclk", "apb_pclk";
354 dmas = <&dmac1 16>, <&dmac1 17>;
355 dma-names = "tx", "rx";
356 pinctrl-names = "default", "high_speed";
357 pinctrl-0 = <&spi2_clk &spi2_csn0 &spi2_miso &spi2_mosi>;
358 pinctrl-1 = <&spi2_clk_hs &spi2_csn0 &spi2_miso_hs &spi2_mosi_hs>;
359 status = "disabled";
360 };
361
362 pwm8: pwm@ff160000 {
363 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
364 reg = <0x0 0xff160000 0x0 0x10>;
365 #pwm-cells = <3>;
366 pinctrl-names = "default";
367 pinctrl-0 = <&pwm8_pin>;
368 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
369 clock-names = "pwm", "pclk";
370 status = "disabled";
371 };
372
373 pwm9: pwm@ff160010 {
374 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
375 reg = <0x0 0xff160010 0x0 0x10>;
376 #pwm-cells = <3>;
377 pinctrl-names = "default";
378 pinctrl-0 = <&pwm9_pin>;
379 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
380 clock-names = "pwm", "pclk";
381 status = "disabled";
382 };
383
384 pwm10: pwm@ff160020 {
385 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
386 reg = <0x0 0xff160020 0x0 0x10>;
387 #pwm-cells = <3>;
388 pinctrl-names = "default";
389 pinctrl-0 = <&pwm10_pin>;
390 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
391 clock-names = "pwm", "pclk";
392 status = "disabled";
393 };
394
395 pwm11: pwm@ff160030 {
396 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
397 reg = <0x0 0xff160030 0x0 0x10>;
398 #pwm-cells = <3>;
399 pinctrl-names = "default";
400 pinctrl-0 = <&pwm11_pin>;
401 clocks = <&cru SCLK_PWM2>, <&cru PCLK_PWM2>;
402 clock-names = "pwm", "pclk";
403 status = "disabled";
404 };
405
406 pwm4: pwm@ff170000 {
407 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
408 reg = <0x0 0xff170000 0x0 0x10>;
409 #pwm-cells = <3>;
410 pinctrl-names = "default";
411 pinctrl-0 = <&pwm4_pin>;
412 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
413 clock-names = "pwm", "pclk";
414 status = "disabled";
415 };
416
417 pwm5: pwm@ff170010 {
418 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
419 reg = <0x0 0xff170010 0x0 0x10>;
420 #pwm-cells = <3>;
421 pinctrl-names = "default";
422 pinctrl-0 = <&pwm5_pin>;
423 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
424 clock-names = "pwm", "pclk";
425 status = "disabled";
426 };
427
428 pwm6: pwm@ff170020 {
429 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
430 reg = <0x0 0xff170020 0x0 0x10>;
431 #pwm-cells = <3>;
432 pinctrl-names = "default";
433 pinctrl-0 = <&pwm6_pin>;
434 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
435 clock-names = "pwm", "pclk";
436 status = "disabled";
437 };
438
439 pwm7: pwm@ff170030 {
440 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
441 reg = <0x0 0xff170030 0x0 0x10>;
442 #pwm-cells = <3>;
443 pinctrl-names = "default";
444 pinctrl-0 = <&pwm7_pin>;
445 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>;
446 clock-names = "pwm", "pclk";
447 status = "disabled";
448 };
449
450 pwm0: pwm@ff180000 {
451 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
452 reg = <0x0 0xff180000 0x0 0x10>;
453 #pwm-cells = <3>;
454 pinctrl-names = "default";
455 pinctrl-0 = <&pwm0_pin>;
456 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
457 clock-names = "pwm", "pclk";
458 status = "disabled";
459 };
460
461 pwm1: pwm@ff180010 {
462 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
463 reg = <0x0 0xff180010 0x0 0x10>;
464 #pwm-cells = <3>;
465 pinctrl-names = "default";
466 pinctrl-0 = <&pwm1_pin>;
467 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
468 clock-names = "pwm", "pclk";
469 status = "disabled";
470 };
471
472 pwm2: pwm@ff180020 {
473 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
474 reg = <0x0 0xff180020 0x0 0x10>;
475 #pwm-cells = <3>;
476 pinctrl-names = "default";
477 pinctrl-0 = <&pwm2_pin>;
478 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
479 clock-names = "pwm", "pclk";
480 status = "disabled";
481 };
482
483 pwm3: pwm@ff180030 {
484 compatible = "rockchip,rk3308-pwm", "rockchip,rk3328-pwm";
485 reg = <0x0 0xff180030 0x0 0x10>;
486 #pwm-cells = <3>;
487 pinctrl-names = "default";
488 pinctrl-0 = <&pwm3_pin>;
489 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
490 clock-names = "pwm", "pclk";
491 status = "disabled";
492 };
493
494 rktimer: rktimer@ff1a0000 {
495 compatible = "rockchip,rk3288-timer";
496 reg = <0x0 0xff1a0000 0x0 0x20>;
497 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
498 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
499 clock-names = "pclk", "timer";
500 };
501
502 saradc: saradc@ff1e0000 {
503 compatible = "rockchip,rk3308-saradc", "rockchip,rk3399-saradc";
504 reg = <0x0 0xff1e0000 0x0 0x100>;
505 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
506 #io-channel-cells = <1>;
507 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
508 clock-names = "saradc", "apb_pclk";
509 resets = <&cru SRST_SARADC_P>;
510 reset-names = "saradc-apb";
511 status = "disabled";
512 };
513
514 amba {
515 compatible = "arm,amba-bus";
516 #address-cells = <2>;
517 #size-cells = <2>;
518 ranges;
519
520 dmac0: dma-controller@ff2c0000 {
521 compatible = "arm,pl330", "arm,primecell";
522 reg = <0x0 0xff2c0000 0x0 0x4000>;
523 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
525 #dma-cells = <1>;
526 clocks = <&cru ACLK_DMAC0>;
527 clock-names = "apb_pclk";
528 peripherals-req-type-burst;
529 };
530
531 dmac1: dma-controller@ff2d0000 {
532 compatible = "arm,pl330", "arm,primecell";
533 reg = <0x0 0xff2d0000 0x0 0x4000>;
534 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
535 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
536 #dma-cells = <1>;
537 clocks = <&cru ACLK_DMAC1>;
538 clock-names = "apb_pclk";
539 peripherals-req-type-burst;
540 };
541 };
542
543 i2s_2ch_0: i2s@ff350000 {
544 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
545 reg = <0x0 0xff350000 0x0 0x1000>;
546 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
547 clocks = <&cru SCLK_I2S0_2CH>, <&cru HCLK_I2S0_2CH>;
548 clock-names = "i2s_clk", "i2s_hclk";
549 dmas = <&dmac1 8>, <&dmac1 9>;
550 dma-names = "tx", "rx";
551 resets = <&cru SRST_I2S0_2CH_M>, <&cru SRST_I2S0_2CH_H>;
552 reset-names = "reset-m", "reset-h";
553 pinctrl-names = "default";
554 pinctrl-0 = <&i2s_2ch_0_sclk
555 &i2s_2ch_0_lrck
556 &i2s_2ch_0_sdi
557 &i2s_2ch_0_sdo>;
558 status = "disabled";
559 };
560
561 i2s_2ch_1: i2s@ff360000 {
562 compatible = "rockchip,rk3308-i2s", "rockchip,rk3066-i2s";
563 reg = <0x0 0xff360000 0x0 0x1000>;
564 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
565 clocks = <&cru SCLK_I2S1_2CH>, <&cru HCLK_I2S1_2CH>;
566 clock-names = "i2s_clk", "i2s_hclk";
567 dmas = <&dmac1 11>;
568 dma-names = "rx";
569 resets = <&cru SRST_I2S1_2CH_M>, <&cru SRST_I2S1_2CH_H>;
570 reset-names = "reset-m", "reset-h";
571 status = "disabled";
572 };
573
574 spdif_tx: spdif-tx@ff3a0000 {
575 compatible = "rockchip,rk3308-spdif", "rockchip,rk3328-spdif";
576 reg = <0x0 0xff3a0000 0x0 0x1000>;
577 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
578 clocks = <&cru SCLK_SPDIF_TX>, <&cru HCLK_SPDIFTX>;
579 clock-names = "mclk", "hclk";
580 dmas = <&dmac1 13>;
581 dma-names = "tx";
582 pinctrl-names = "default";
583 pinctrl-0 = <&spdif_out>;
584 status = "disabled";
585 };
586
587 sdmmc: dwmmc@ff480000 {
588 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
589 reg = <0x0 0xff480000 0x0 0x4000>;
590 max-frequency = <150000000>;
591 bus-width = <4>;
592 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
593 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
594 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
595 fifo-depth = <0x100>;
596 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
597 pinctrl-names = "default";
598 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
599 status = "disabled";
600 };
601
602 emmc: dwmmc@ff490000 {
603 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
604 reg = <0x0 0xff490000 0x0 0x4000>;
605 max-frequency = <150000000>;
606 bus-width = <8>;
607 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
608 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
609 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
610 fifo-depth = <0x100>;
611 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
612 status = "disabled";
613 };
614
615 sdio: dwmmc@ff4a0000 {
616 compatible = "rockchip,rk3308-dw-mshc", "rockchip,rk3288-dw-mshc";
617 reg = <0x0 0xff4a0000 0x0 0x4000>;
618 max-frequency = <150000000>;
619 bus-width = <4>;
620 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
621 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
622 clock-names = "biu", "ciu", "ciu-drv", "ciu-sample";
623 fifo-depth = <0x100>;
624 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
625 pinctrl-names = "default";
626 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>;
627 status = "disabled";
628 };
629
630 cru: clock-controller@ff500000 {
631 compatible = "rockchip,rk3308-cru";
632 reg = <0x0 0xff500000 0x0 0x1000>;
633 rockchip,grf = <&grf>;
634 #clock-cells = <1>;
635 #reset-cells = <1>;
636 };
637
638 gic: interrupt-controller@ff580000 {
639 compatible = "arm,gic-400";
640 #interrupt-cells = <3>;
641 #address-cells = <0>;
642 interrupt-controller;
643
644 reg = <0x0 0xff581000 0x0 0x1000>,
645 <0x0 0xff582000 0x0 0x2000>,
646 <0x0 0xff584000 0x0 0x2000>,
647 <0x0 0xff586000 0x0 0x2000>;
648 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
649 };
650
651 sram: sram@fff80000 {
652 compatible = "mmio-sram";
653 reg = <0x0 0xfff80000 0x0 0x40000>;
654 #address-cells = <1>;
655 #size-cells = <1>;
656 ranges = <0 0x0 0xfff80000 0x40000>;
657 /* reserved for ddr dvfs and system suspend/resume */
658 ddr-sram@0 {
659 reg = <0x0 0x8000>;
660 };
661 /* reserved for vad audio buffer */
662 vad_sram: vad-sram@8000 {
663 reg = <0x8000 0x38000>;
664 };
665 };
666
667 pinctrl: pinctrl {
668 compatible = "rockchip,rk3308-pinctrl";
669 rockchip,grf = <&grf>;
670 #address-cells = <2>;
671 #size-cells = <2>;
672 ranges;
673 gpio0: gpio0@ff220000 {
674 compatible = "rockchip,gpio-bank";
675 reg = <0x0 0xff220000 0x0 0x100>;
676 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
677 clocks = <&cru PCLK_GPIO0>;
678 gpio-controller;
679 #gpio-cells = <2>;
680
681 interrupt-controller;
682 #interrupt-cells = <2>;
683 };
684
685 gpio1: gpio1@ff230000 {
686 compatible = "rockchip,gpio-bank";
687 reg = <0x0 0xff230000 0x0 0x100>;
688 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
689 clocks = <&cru PCLK_GPIO1>;
690 gpio-controller;
691 #gpio-cells = <2>;
692
693 interrupt-controller;
694 #interrupt-cells = <2>;
695 };
696
697 gpio2: gpio2@ff240000 {
698 compatible = "rockchip,gpio-bank";
699 reg = <0x0 0xff240000 0x0 0x100>;
700 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
701 clocks = <&cru PCLK_GPIO2>;
702 gpio-controller;
703 #gpio-cells = <2>;
704
705 interrupt-controller;
706 #interrupt-cells = <2>;
707 };
708
709 gpio3: gpio3@ff250000 {
710 compatible = "rockchip,gpio-bank";
711 reg = <0x0 0xff250000 0x0 0x100>;
712 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
713 clocks = <&cru PCLK_GPIO3>;
714 gpio-controller;
715 #gpio-cells = <2>;
716
717 interrupt-controller;
718 #interrupt-cells = <2>;
719 };
720
721 gpio4: gpio4@ff260000 {
722 compatible = "rockchip,gpio-bank";
723 reg = <0x0 0xff260000 0x0 0x100>;
724 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
725 clocks = <&cru PCLK_GPIO4>;
726 gpio-controller;
727 #gpio-cells = <2>;
728
729 interrupt-controller;
730 #interrupt-cells = <2>;
731 };
732
733 pcfg_pull_up: pcfg-pull-up {
734 bias-pull-up;
735 };
736
737 pcfg_pull_down: pcfg-pull-down {
738 bias-pull-down;
739 };
740
741 pcfg_pull_none: pcfg-pull-none {
742 bias-disable;
743 };
744
745 pcfg_pull_none_2ma: pcfg-pull-none-2ma {
746 bias-disable;
747 drive-strength = <2>;
748 };
749
750 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
751 bias-pull-up;
752 drive-strength = <2>;
753 };
754
755 pcfg_pull_up_4ma: pcfg-pull-up-4ma {
756 bias-pull-up;
757 drive-strength = <4>;
758 };
759
760 pcfg_pull_none_4ma: pcfg-pull-none-4ma {
761 bias-disable;
762 drive-strength = <4>;
763 };
764
765 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
766 bias-pull-down;
767 drive-strength = <4>;
768 };
769
770 pcfg_pull_none_8ma: pcfg-pull-none-8ma {
771 bias-disable;
772 drive-strength = <8>;
773 };
774
775 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
776 bias-pull-up;
777 drive-strength = <8>;
778 };
779
780 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
781 bias-disable;
782 drive-strength = <12>;
783 };
784
785 pcfg_pull_up_12ma: pcfg-pull-up-12ma {
786 bias-pull-up;
787 drive-strength = <12>;
788 };
789
790 pcfg_pull_none_smt: pcfg-pull-none-smt {
791 bias-disable;
792 input-schmitt-enable;
793 };
794
795 pcfg_output_high: pcfg-output-high {
796 output-high;
797 };
798
799 pcfg_output_low: pcfg-output-low {
800 output-low;
801 };
802
803 pcfg_input_high: pcfg-input-high {
804 bias-pull-up;
805 input-enable;
806 };
807
808 pcfg_input: pcfg-input {
809 input-enable;
810 };
811
812 i2c0 {
813 i2c0_xfer: i2c0-xfer {
814 rockchip,pins =
815 <1 RK_PD0 2 &pcfg_pull_none_smt>,
816 <1 RK_PD1 2 &pcfg_pull_none_smt>;
817 };
818 };
819
820 i2c1 {
821 i2c1_xfer: i2c1-xfer {
822 rockchip,pins =
823 <0 RK_PB3 1 &pcfg_pull_none_smt>,
824 <0 RK_PB4 1 &pcfg_pull_none_smt>;
825 };
826 };
827
828 i2c2 {
829 i2c2_xfer: i2c2-xfer {
830 rockchip,pins =
831 <2 RK_PA2 3 &pcfg_pull_none_smt>,
832 <2 RK_PA3 3 &pcfg_pull_none_smt>;
833 };
834 };
835
836 i2c3-m0 {
837 i2c3m0_xfer: i2c3m0-xfer {
838 rockchip,pins =
839 <0 RK_PB7 2 &pcfg_pull_none_smt>,
840 <0 RK_PC0 2 &pcfg_pull_none_smt>;
841 };
842 };
843
844 i2c3-m1 {
845 i2c3m1_xfer: i2c3m1-xfer {
846 rockchip,pins =
847 <3 RK_PB4 2 &pcfg_pull_none_smt>,
848 <3 RK_PB5 2 &pcfg_pull_none_smt>;
849 };
850 };
851
852 i2c3-m2 {
853 i2c3m2_xfer: i2c3m2-xfer {
854 rockchip,pins =
855 <2 RK_PA1 3 &pcfg_pull_none_smt>,
856 <2 RK_PA0 3 &pcfg_pull_none_smt>;
857 };
858 };
859
860 i2s_2ch_0 {
861 i2s_2ch_0_mclk: i2s-2ch-0-mclk {
862 rockchip,pins =
863 <4 RK_PB4 1 &pcfg_pull_none>;
864 };
865
866 i2s_2ch_0_sclk: i2s-2ch-0-sclk {
867 rockchip,pins =
868 <4 RK_PB5 1 &pcfg_pull_none>;
869 };
870
871 i2s_2ch_0_lrck: i2s-2ch-0-lrck {
872 rockchip,pins =
873 <4 RK_PB6 1 &pcfg_pull_none>;
874 };
875
876 i2s_2ch_0_sdo: i2s-2ch-0-sdo {
877 rockchip,pins =
878 <4 RK_PB7 1 &pcfg_pull_none>;
879 };
880
881 i2s_2ch_0_sdi: i2s-2ch-0-sdi {
882 rockchip,pins =
883 <4 RK_PC0 1 &pcfg_pull_none>;
884 };
885 };
886
887 i2s_8ch_0 {
888 i2s_8ch_0_mclk: i2s-8ch-0-mclk {
889 rockchip,pins =
890 <2 RK_PA4 1 &pcfg_pull_none>;
891 };
892
893 i2s_8ch_0_sclktx: i2s-8ch-0-sclktx {
894 rockchip,pins =
895 <2 RK_PA5 1 &pcfg_pull_none>;
896 };
897
898 i2s_8ch_0_sclkrx: i2s-8ch-0-sclkrx {
899 rockchip,pins =
900 <2 RK_PA6 1 &pcfg_pull_none>;
901 };
902
903 i2s_8ch_0_lrcktx: i2s-8ch-0-lrcktx {
904 rockchip,pins =
905 <2 RK_PA7 1 &pcfg_pull_none>;
906 };
907
908 i2s_8ch_0_lrckrx: i2s-8ch-0-lrckrx {
909 rockchip,pins =
910 <2 RK_PB0 1 &pcfg_pull_none>;
911 };
912
913 i2s_8ch_0_sdo0: i2s-8ch-0-sdo0 {
914 rockchip,pins =
915 <2 RK_PB1 1 &pcfg_pull_none>;
916 };
917
918 i2s_8ch_0_sdo1: i2s-8ch-0-sdo1 {
919 rockchip,pins =
920 <2 RK_PB2 1 &pcfg_pull_none>;
921 };
922
923 i2s_8ch_0_sdo2: i2s-8ch-0-sdo2 {
924 rockchip,pins =
925 <2 RK_PB3 1 &pcfg_pull_none>;
926 };
927
928 i2s_8ch_0_sdo3: i2s-8ch-0-sdo3 {
929 rockchip,pins =
930 <2 RK_PB4 1 &pcfg_pull_none>;
931 };
932
933 i2s_8ch_0_sdi0: i2s-8ch-0-sdi0 {
934 rockchip,pins =
935 <2 RK_PB5 1 &pcfg_pull_none>;
936 };
937
938 i2s_8ch_0_sdi1: i2s-8ch-0-sdi1 {
939 rockchip,pins =
940 <2 RK_PB6 1 &pcfg_pull_none>;
941 };
942
943 i2s_8ch_0_sdi2: i2s-8ch-0-sdi2 {
944 rockchip,pins =
945 <2 RK_PB7 1 &pcfg_pull_none>;
946 };
947
948 i2s_8ch_0_sdi3: i2s-8ch-0-sdi3 {
949 rockchip,pins =
950 <2 RK_PC0 1 &pcfg_pull_none>;
951 };
952 };
953
954 i2s_8ch_1_m0 {
955 i2s_8ch_1_m0_mclk: i2s-8ch-1-m0-mclk {
956 rockchip,pins =
957 <1 RK_PA2 2 &pcfg_pull_none>;
958 };
959
960 i2s_8ch_1_m0_sclktx: i2s-8ch-1-m0-sclktx {
961 rockchip,pins =
962 <1 RK_PA3 2 &pcfg_pull_none>;
963 };
964
965 i2s_8ch_1_m0_sclkrx: i2s-8ch-1-m0-sclkrx {
966 rockchip,pins =
967 <1 RK_PA4 2 &pcfg_pull_none>;
968 };
969
970 i2s_8ch_1_m0_lrcktx: i2s-8ch-1-m0-lrcktx {
971 rockchip,pins =
972 <1 RK_PA5 2 &pcfg_pull_none>;
973 };
974
975 i2s_8ch_1_m0_lrckrx: i2s-8ch-1-m0-lrckrx {
976 rockchip,pins =
977 <1 RK_PA6 2 &pcfg_pull_none>;
978 };
979
980 i2s_8ch_1_m0_sdo0: i2s-8ch-1-m0-sdo0 {
981 rockchip,pins =
982 <1 RK_PA7 2 &pcfg_pull_none>;
983 };
984
985 i2s_8ch_1_m0_sdo1_sdi3: i2s-8ch-1-m0-sdo1-sdi3 {
986 rockchip,pins =
987 <1 RK_PB0 2 &pcfg_pull_none>;
988 };
989
990 i2s_8ch_1_m0_sdo2_sdi2: i2s-8ch-1-m0-sdo2-sdi2 {
991 rockchip,pins =
992 <1 RK_PB1 2 &pcfg_pull_none>;
993 };
994
995 i2s_8ch_1_m0_sdo3_sdi1: i2s-8ch-1-m0-sdo3_sdi1 {
996 rockchip,pins =
997 <1 RK_PB2 2 &pcfg_pull_none>;
998 };
999
1000 i2s_8ch_1_m0_sdi0: i2s-8ch-1-m0-sdi0 {
1001 rockchip,pins =
1002 <1 RK_PB3 2 &pcfg_pull_none>;
1003 };
1004 };
1005
1006 i2s_8ch_1_m1 {
1007 i2s_8ch_1_m1_mclk: i2s-8ch-1-m1-mclk {
1008 rockchip,pins =
1009 <1 RK_PB4 2 &pcfg_pull_none>;
1010 };
1011
1012 i2s_8ch_1_m1_sclktx: i2s-8ch-1-m1-sclktx {
1013 rockchip,pins =
1014 <1 RK_PB5 2 &pcfg_pull_none>;
1015 };
1016
1017 i2s_8ch_1_m1_sclkrx: i2s-8ch-1-m1-sclkrx {
1018 rockchip,pins =
1019 <1 RK_PB6 2 &pcfg_pull_none>;
1020 };
1021
1022 i2s_8ch_1_m1_lrcktx: i2s-8ch-1-m1-lrcktx {
1023 rockchip,pins =
1024 <1 RK_PB7 2 &pcfg_pull_none>;
1025 };
1026
1027 i2s_8ch_1_m1_lrckrx: i2s-8ch-1-m1-lrckrx {
1028 rockchip,pins =
1029 <1 RK_PC0 2 &pcfg_pull_none>;
1030 };
1031
1032 i2s_8ch_1_m1_sdo0: i2s-8ch-1-m1-sdo0 {
1033 rockchip,pins =
1034 <1 RK_PC1 2 &pcfg_pull_none>;
1035 };
1036
1037 i2s_8ch_1_m1_sdo1_sdi3: i2s-8ch-1-m1-sdo1-sdi3 {
1038 rockchip,pins =
1039 <1 RK_PC2 2 &pcfg_pull_none>;
1040 };
1041
1042 i2s_8ch_1_m1_sdo2_sdi2: i2s-8ch-1-m1-sdo2-sdi2 {
1043 rockchip,pins =
1044 <1 RK_PC3 2 &pcfg_pull_none>;
1045 };
1046
1047 i2s_8ch_1_m1_sdo3_sdi1: i2s-8ch-1-m1-sdo3_sdi1 {
1048 rockchip,pins =
1049 <1 RK_PC4 2 &pcfg_pull_none>;
1050 };
1051
1052 i2s_8ch_1_m1_sdi0: i2s-8ch-1-m1-sdi0 {
1053 rockchip,pins =
1054 <1 RK_PC5 2 &pcfg_pull_none>;
1055 };
1056 };
1057
1058 pdm_m0 {
1059 pdm_m0_clk: pdm-m0-clk {
1060 rockchip,pins =
1061 <1 RK_PA4 3 &pcfg_pull_none>;
1062 };
1063
1064 pdm_m0_sdi0: pdm-m0-sdi0 {
1065 rockchip,pins =
1066 <1 RK_PB3 3 &pcfg_pull_none>;
1067 };
1068
1069 pdm_m0_sdi1: pdm-m0-sdi1 {
1070 rockchip,pins =
1071 <1 RK_PB2 3 &pcfg_pull_none>;
1072 };
1073
1074 pdm_m0_sdi2: pdm-m0-sdi2 {
1075 rockchip,pins =
1076 <1 RK_PB1 3 &pcfg_pull_none>;
1077 };
1078
1079 pdm_m0_sdi3: pdm-m0-sdi3 {
1080 rockchip,pins =
1081 <1 RK_PB0 3 &pcfg_pull_none>;
1082 };
1083 };
1084
1085 pdm_m1 {
1086 pdm_m1_clk: pdm-m1-clk {
1087 rockchip,pins =
1088 <1 RK_PB6 4 &pcfg_pull_none>;
1089 };
1090
1091 pdm_m1_sdi0: pdm-m1-sdi0 {
1092 rockchip,pins =
1093 <1 RK_PC5 4 &pcfg_pull_none>;
1094 };
1095
1096 pdm_m1_sdi1: pdm-m1-sdi1 {
1097 rockchip,pins =
1098 <1 RK_PC4 4 &pcfg_pull_none>;
1099 };
1100
1101 pdm_m1_sdi2: pdm-m1-sdi2 {
1102 rockchip,pins =
1103 <1 RK_PC3 4 &pcfg_pull_none>;
1104 };
1105
1106 pdm_m1_sdi3: pdm-m1-sdi3 {
1107 rockchip,pins =
1108 <1 RK_PC2 4 &pcfg_pull_none>;
1109 };
1110 };
1111
1112 pdm_m2 {
1113 pdm_m2_clkm: pdm-m2-clkm {
1114 rockchip,pins =
1115 <2 RK_PA4 3 &pcfg_pull_none>;
1116 };
1117
1118 pdm_m2_clk: pdm-m2-clk {
1119 rockchip,pins =
1120 <2 RK_PA6 2 &pcfg_pull_none>;
1121 };
1122
1123 pdm_m2_sdi0: pdm-m2-sdi0 {
1124 rockchip,pins =
1125 <2 RK_PB5 2 &pcfg_pull_none>;
1126 };
1127
1128 pdm_m2_sdi1: pdm-m2-sdi1 {
1129 rockchip,pins =
1130 <2 RK_PB6 2 &pcfg_pull_none>;
1131 };
1132
1133 pdm_m2_sdi2: pdm-m2-sdi2 {
1134 rockchip,pins =
1135 <2 RK_PB7 2 &pcfg_pull_none>;
1136 };
1137
1138 pdm_m2_sdi3: pdm-m2-sdi3 {
1139 rockchip,pins =
1140 <2 RK_PC0 2 &pcfg_pull_none>;
1141 };
1142 };
1143
1144 spdif_in {
1145 spdif_in: spdif-in {
1146 rockchip,pins =
1147 <0 RK_PC2 1 &pcfg_pull_none>;
1148 };
1149 };
1150
1151 spdif_out {
1152 spdif_out: spdif-out {
1153 rockchip,pins =
1154 <0 RK_PC1 1 &pcfg_pull_none>;
1155 };
1156 };
1157
1158 tsadc {
1159 tsadc_otp_gpio: tsadc-otp-gpio {
1160 rockchip,pins =
1161 <0 RK_PB2 0 &pcfg_pull_none>;
1162 };
1163
1164 tsadc_otp_out: tsadc-otp-out {
1165 rockchip,pins =
1166 <0 RK_PB2 1 &pcfg_pull_none>;
1167 };
1168 };
1169
1170 uart0 {
1171 uart0_xfer: uart0-xfer {
1172 rockchip,pins =
1173 <2 RK_PA1 1 &pcfg_pull_up>,
1174 <2 RK_PA0 1 &pcfg_pull_up>;
1175 };
1176
1177 uart0_cts: uart0-cts {
1178 rockchip,pins =
1179 <2 RK_PA2 1 &pcfg_pull_none>;
1180 };
1181
1182 uart0_rts: uart0-rts {
1183 rockchip,pins =
1184 <2 RK_PA3 1 &pcfg_pull_none>;
1185 };
1186
1187 uart0_rts_gpio: uart0-rts-gpio {
1188 rockchip,pins =
1189 <2 RK_PA3 0 &pcfg_pull_none>;
1190 };
1191 };
1192
1193 uart1 {
1194 uart1_xfer: uart1-xfer {
1195 rockchip,pins =
1196 <1 RK_PD1 1 &pcfg_pull_up>,
1197 <1 RK_PD0 1 &pcfg_pull_up>;
1198 };
1199
1200 uart1_cts: uart1-cts {
1201 rockchip,pins =
1202 <1 RK_PC6 1 &pcfg_pull_none>;
1203 };
1204
1205 uart1_rts: uart1-rts {
1206 rockchip,pins =
1207 <1 RK_PC7 1 &pcfg_pull_none>;
1208 };
1209 };
1210
1211 uart2-m0 {
1212 uart2m0_xfer: uart2m0-xfer {
1213 rockchip,pins =
1214 <1 RK_PC7 2 &pcfg_pull_up>,
1215 <1 RK_PC6 2 &pcfg_pull_up>;
1216 };
1217 };
1218
1219 uart2-m1 {
1220 uart2m1_xfer: uart2m1-xfer {
1221 rockchip,pins =
1222 <4 RK_PD3 2 &pcfg_pull_up>,
1223 <4 RK_PD2 2 &pcfg_pull_up>;
1224 };
1225 };
1226
1227 uart3 {
1228 uart3_xfer: uart3-xfer {
1229 rockchip,pins =
1230 <3 RK_PB5 4 &pcfg_pull_up>,
1231 <3 RK_PB4 4 &pcfg_pull_up>;
1232 };
1233 };
1234
1235 uart3-m1 {
1236 uart3m1_xfer: uart3m1-xfer {
1237 rockchip,pins =
1238 <0 RK_PC2 3 &pcfg_pull_up>,
1239 <0 RK_PC1 3 &pcfg_pull_up>;
1240 };
1241 };
1242
1243 uart4 {
1244
1245 uart4_xfer: uart4-xfer {
1246 rockchip,pins =
1247 <4 RK_PB1 1 &pcfg_pull_up>,
1248 <4 RK_PB0 1 &pcfg_pull_up>;
1249 };
1250
1251 uart4_cts: uart4-cts {
1252 rockchip,pins =
1253 <4 RK_PA6 1 &pcfg_pull_none>;
1254
1255 };
1256
1257 uart4_rts: uart4-rts {
1258 rockchip,pins =
1259 <4 RK_PA7 1 &pcfg_pull_none>;
1260 };
1261
1262 uart4_rts_gpio: uart4-rts-gpio {
1263 rockchip,pins =
1264 <4 RK_PA7 0 &pcfg_pull_none>;
1265 };
1266 };
1267
1268 spi0 {
1269 spi0_clk: spi0-clk {
1270 rockchip,pins =
1271 <2 RK_PA2 2 &pcfg_pull_up_4ma>;
1272 };
1273
1274 spi0_csn0: spi0-csn0 {
1275 rockchip,pins =
1276 <2 RK_PA3 2 &pcfg_pull_up_4ma>;
1277 };
1278
1279 spi0_miso: spi0-miso {
1280 rockchip,pins =
1281 <2 RK_PA0 2 &pcfg_pull_up_4ma>;
1282 };
1283
1284 spi0_mosi: spi0-mosi {
1285 rockchip,pins =
1286 <2 RK_PA1 2 &pcfg_pull_up_4ma>;
1287 };
1288
1289 spi0_clk_hs: spi0-clk-hs {
1290 rockchip,pins =
1291 <2 RK_PA2 2 &pcfg_pull_up_8ma>;
1292 };
1293
1294 spi0_miso_hs: spi0-miso-hs {
1295 rockchip,pins =
1296 <2 RK_PA0 2 &pcfg_pull_up_8ma>;
1297 };
1298
1299 spi0_mosi_hs: spi0-mosi-hs {
1300 rockchip,pins =
1301 <2 RK_PA1 2 &pcfg_pull_up_8ma>;
1302 };
1303
1304 };
1305
1306 spi1 {
1307 spi1_clk: spi1-clk {
1308 rockchip,pins =
1309 <3 RK_PB3 3 &pcfg_pull_up_4ma>;
1310 };
1311
1312 spi1_csn0: spi1-csn0 {
1313 rockchip,pins =
1314 <3 RK_PB5 3 &pcfg_pull_up_4ma>;
1315 };
1316
1317 spi1_miso: spi1-miso {
1318 rockchip,pins =
1319 <3 RK_PB2 3 &pcfg_pull_up_4ma>;
1320 };
1321
1322 spi1_mosi: spi1-mosi {
1323 rockchip,pins =
1324 <3 RK_PB4 3 &pcfg_pull_up_4ma>;
1325 };
1326
1327 spi1_clk_hs: spi1-clk-hs {
1328 rockchip,pins =
1329 <3 RK_PB3 3 &pcfg_pull_up_8ma>;
1330 };
1331
1332 spi1_miso_hs: spi1-miso-hs {
1333 rockchip,pins =
1334 <3 RK_PB2 3 &pcfg_pull_up_8ma>;
1335 };
1336
1337 spi1_mosi_hs: spi1-mosi-hs {
1338 rockchip,pins =
1339 <3 RK_PB4 3 &pcfg_pull_up_8ma>;
1340 };
1341 };
1342
1343 spi1-m1 {
1344 spi1m1_miso: spi1m1-miso {
1345 rockchip,pins =
1346 <2 RK_PA4 2 &pcfg_pull_up_4ma>;
1347 };
1348
1349 spi1m1_mosi: spi1m1-mosi {
1350 rockchip,pins =
1351 <2 RK_PA5 2 &pcfg_pull_up_4ma>;
1352 };
1353
1354 spi1m1_clk: spi1m1-clk {
1355 rockchip,pins =
1356 <2 RK_PA7 2 &pcfg_pull_up_4ma>;
1357 };
1358
1359 spi1m1_csn0: spi1m1-csn0 {
1360 rockchip,pins =
1361 <2 RK_PB1 2 &pcfg_pull_up_4ma>;
1362 };
1363
1364 spi1m1_miso_hs: spi1m1-miso-hs {
1365 rockchip,pins =
1366 <2 RK_PA4 2 &pcfg_pull_up_8ma>;
1367 };
1368
1369 spi1m1_mosi_hs: spi1m1-mosi-hs {
1370 rockchip,pins =
1371 <2 RK_PA5 2 &pcfg_pull_up_8ma>;
1372 };
1373
1374 spi1m1_clk_hs: spi1m1-clk-hs {
1375 rockchip,pins =
1376 <2 RK_PA7 2 &pcfg_pull_up_8ma>;
1377 };
1378
1379 spi1m1_csn0_hs: spi1m1-csn0-hs {
1380 rockchip,pins =
1381 <2 RK_PB1 2 &pcfg_pull_up_8ma>;
1382 };
1383 };
1384
1385 spi2 {
1386 spi2_clk: spi2-clk {
1387 rockchip,pins =
1388 <1 RK_PD0 3 &pcfg_pull_up_4ma>;
1389 };
1390
1391 spi2_csn0: spi2-csn0 {
1392 rockchip,pins =
1393 <1 RK_PD1 3 &pcfg_pull_up_4ma>;
1394 };
1395
1396 spi2_miso: spi2-miso {
1397 rockchip,pins =
1398 <1 RK_PC6 3 &pcfg_pull_up_4ma>;
1399 };
1400
1401 spi2_mosi: spi2-mosi {
1402 rockchip,pins =
1403 <1 RK_PC7 3 &pcfg_pull_up_4ma>;
1404 };
1405
1406 spi2_clk_hs: spi2-clk-hs {
1407 rockchip,pins =
1408 <1 RK_PD0 3 &pcfg_pull_up_8ma>;
1409 };
1410
1411 spi2_miso_hs: spi2-miso-hs {
1412 rockchip,pins =
1413 <1 RK_PC6 3 &pcfg_pull_up_8ma>;
1414 };
1415
1416 spi2_mosi_hs: spi2-mosi-hs {
1417 rockchip,pins =
1418 <1 RK_PC7 3 &pcfg_pull_up_8ma>;
1419 };
1420 };
1421
1422 sdmmc {
1423 sdmmc_clk: sdmmc-clk {
1424 rockchip,pins =
1425 <4 RK_PD5 1 &pcfg_pull_none_4ma>;
1426 };
1427
1428 sdmmc_cmd: sdmmc-cmd {
1429 rockchip,pins =
1430 <4 RK_PD4 1 &pcfg_pull_up_4ma>;
1431 };
1432
1433 sdmmc_det: sdmmc-det {
1434 rockchip,pins =
1435 <0 RK_PA3 1 &pcfg_pull_up_4ma>;
1436 };
1437
1438 sdmmc_pwren: sdmmc-pwren {
1439 rockchip,pins =
1440 <4 RK_PD6 1 &pcfg_pull_none_4ma>;
1441 };
1442
1443 sdmmc_bus1: sdmmc-bus1 {
1444 rockchip,pins =
1445 <4 RK_PD0 1 &pcfg_pull_up_4ma>;
1446 };
1447
1448 sdmmc_bus4: sdmmc-bus4 {
1449 rockchip,pins =
1450 <4 RK_PD0 1 &pcfg_pull_up_4ma>,
1451 <4 RK_PD1 1 &pcfg_pull_up_4ma>,
1452 <4 RK_PD2 1 &pcfg_pull_up_4ma>,
1453 <4 RK_PD3 1 &pcfg_pull_up_4ma>;
1454 };
1455
1456 sdmmc_gpio: sdmmc-gpio {
1457 rockchip,pins =
1458 <4 RK_PD0 0 &pcfg_pull_up_4ma>,
1459 <4 RK_PD1 0 &pcfg_pull_up_4ma>,
1460 <4 RK_PD2 0 &pcfg_pull_up_4ma>,
1461 <4 RK_PD3 0 &pcfg_pull_up_4ma>,
1462 <4 RK_PD4 0 &pcfg_pull_up_4ma>,
1463 <4 RK_PD5 0 &pcfg_pull_up_4ma>,
1464 <4 RK_PD6 0 &pcfg_pull_up_4ma>;
1465 };
1466 };
1467
1468 sdio {
1469 sdio_clk: sdio-clk {
1470 rockchip,pins =
1471 <4 RK_PA5 1 &pcfg_pull_none_8ma>;
1472 };
1473
1474 sdio_cmd: sdio-cmd {
1475 rockchip,pins =
1476 <4 RK_PA4 1 &pcfg_pull_up_8ma>;
1477 };
1478
1479 sdio_pwren: sdio-pwren {
1480 rockchip,pins =
1481 <0 RK_PA2 1 &pcfg_pull_none_8ma>;
1482 };
1483
1484 sdio_wrpt: sdio-wrpt {
1485 rockchip,pins =
1486 <0 RK_PA1 1 &pcfg_pull_none_8ma>;
1487 };
1488
1489 sdio_intn: sdio-intn {
1490 rockchip,pins =
1491 <0 RK_PA0 1 &pcfg_pull_none_8ma>;
1492 };
1493
1494 sdio_bus1: sdio-bus1 {
1495 rockchip,pins =
1496 <4 RK_PA0 1 &pcfg_pull_up_8ma>;
1497 };
1498
1499 sdio_bus4: sdio-bus4 {
1500 rockchip,pins =
1501 <4 RK_PA0 1 &pcfg_pull_up_8ma>,
1502 <4 RK_PA1 1 &pcfg_pull_up_8ma>,
1503 <4 RK_PA2 1 &pcfg_pull_up_8ma>,
1504 <4 RK_PA3 1 &pcfg_pull_up_8ma>;
1505 };
1506
1507 sdio_gpio: sdio-gpio {
1508 rockchip,pins =
1509 <4 RK_PA0 0 &pcfg_pull_up_4ma>,
1510 <4 RK_PA1 0 &pcfg_pull_up_4ma>,
1511 <4 RK_PA2 0 &pcfg_pull_up_4ma>,
1512 <4 RK_PA3 0 &pcfg_pull_up_4ma>,
1513 <4 RK_PA4 0 &pcfg_pull_up_4ma>,
1514 <4 RK_PA5 0 &pcfg_pull_up_4ma>;
1515 };
1516 };
1517
1518 emmc {
1519 emmc_clk: emmc-clk {
1520 rockchip,pins =
1521 <3 RK_PB1 2 &pcfg_pull_none_8ma>;
1522 };
1523
1524 emmc_cmd: emmc-cmd {
1525 rockchip,pins =
1526 <3 RK_PB0 2 &pcfg_pull_up_8ma>;
1527 };
1528
1529 emmc_pwren: emmc-pwren {
1530 rockchip,pins =
1531 <3 RK_PB3 2 &pcfg_pull_none>;
1532 };
1533
1534 emmc_rstn: emmc-rstn {
1535 rockchip,pins =
1536 <3 RK_PB2 2 &pcfg_pull_none>;
1537 };
1538
1539 emmc_bus1: emmc-bus1 {
1540 rockchip,pins =
1541 <3 RK_PA0 2 &pcfg_pull_up_8ma>;
1542 };
1543
1544 emmc_bus4: emmc-bus4 {
1545 rockchip,pins =
1546 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
1547 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
1548 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
1549 <3 RK_PA3 2 &pcfg_pull_up_8ma>;
1550 };
1551
1552 emmc_bus8: emmc-bus8 {
1553 rockchip,pins =
1554 <3 RK_PA0 2 &pcfg_pull_up_8ma>,
1555 <3 RK_PA1 2 &pcfg_pull_up_8ma>,
1556 <3 RK_PA2 2 &pcfg_pull_up_8ma>,
1557 <3 RK_PA3 2 &pcfg_pull_up_8ma>,
1558 <3 RK_PA4 2 &pcfg_pull_up_8ma>,
1559 <3 RK_PA5 2 &pcfg_pull_up_8ma>,
1560 <3 RK_PA6 2 &pcfg_pull_up_8ma>,
1561 <3 RK_PA7 2 &pcfg_pull_up_8ma>;
1562 };
1563 };
1564
1565 flash {
1566 flash_csn0: flash-csn0 {
1567 rockchip,pins =
1568 <3 RK_PB5 1 &pcfg_pull_none>;
1569 };
1570
1571 flash_rdy: flash-rdy {
1572 rockchip,pins =
1573 <3 RK_PB4 1 &pcfg_pull_none>;
1574 };
1575
1576 flash_ale: flash-ale {
1577 rockchip,pins =
1578 <3 RK_PB3 1 &pcfg_pull_none>;
1579 };
1580
1581 flash_cle: flash-cle {
1582 rockchip,pins =
1583 <3 RK_PB1 1 &pcfg_pull_none>;
1584 };
1585
1586 flash_wrn: flash-wrn {
1587 rockchip,pins =
1588 <3 RK_PB0 1 &pcfg_pull_none>;
1589 };
1590
1591 flash_rdn: flash-rdn {
1592 rockchip,pins =
1593 <3 RK_PB2 1 &pcfg_pull_none>;
1594 };
1595
1596 flash_bus8: flash-bus8 {
1597 rockchip,pins =
1598 <3 RK_PA0 1 &pcfg_pull_up_12ma>,
1599 <3 RK_PA1 1 &pcfg_pull_up_12ma>,
1600 <3 RK_PA2 1 &pcfg_pull_up_12ma>,
1601 <3 RK_PA3 1 &pcfg_pull_up_12ma>,
1602 <3 RK_PA4 1 &pcfg_pull_up_12ma>,
1603 <3 RK_PA5 1 &pcfg_pull_up_12ma>,
1604 <3 RK_PA6 1 &pcfg_pull_up_12ma>,
1605 <3 RK_PA7 1 &pcfg_pull_up_12ma>;
1606 };
1607 };
1608
1609 pwm0 {
1610 pwm0_pin: pwm0-pin {
1611 rockchip,pins =
1612 <0 RK_PB5 1 &pcfg_pull_none>;
1613 };
1614
1615 pwm0_pin_pull_down: pwm0-pin-pull-down {
1616 rockchip,pins =
1617 <0 RK_PB5 1 &pcfg_pull_down>;
1618 };
1619 };
1620
1621 pwm1 {
1622 pwm1_pin: pwm1-pin {
1623 rockchip,pins =
1624 <0 RK_PB6 1 &pcfg_pull_none>;
1625 };
1626
1627 pwm1_pin_pull_down: pwm1-pin-pull-down {
1628 rockchip,pins =
1629 <0 RK_PB6 1 &pcfg_pull_down>;
1630 };
1631 };
1632
1633 pwm2 {
1634 pwm2_pin: pwm2-pin {
1635 rockchip,pins =
1636 <0 RK_PB7 1 &pcfg_pull_none>;
1637 };
1638
1639 pwm2_pin_pull_down: pwm2-pin-pull-down {
1640 rockchip,pins =
1641 <0 RK_PB7 1 &pcfg_pull_down>;
1642 };
1643 };
1644
1645 pwm3 {
1646 pwm3_pin: pwm3-pin {
1647 rockchip,pins =
1648 <0 RK_PC0 1 &pcfg_pull_none>;
1649 };
1650
1651 pwm3_pin_pull_down: pwm3-pin-pull-down {
1652 rockchip,pins =
1653 <0 RK_PC0 1 &pcfg_pull_down>;
1654 };
1655 };
1656
1657 pwm4 {
1658 pwm4_pin: pwm4-pin {
1659 rockchip,pins =
1660 <0 RK_PA1 2 &pcfg_pull_none>;
1661 };
1662
1663 pwm4_pin_pull_down: pwm4-pin-pull-down {
1664 rockchip,pins =
1665 <0 RK_PA1 2 &pcfg_pull_down>;
1666 };
1667 };
1668
1669 pwm5 {
1670 pwm5_pin: pwm5-pin {
1671 rockchip,pins =
1672 <0 RK_PC1 2 &pcfg_pull_none>;
1673 };
1674
1675 pwm5_pin_pull_down: pwm5-pin-pull-down {
1676 rockchip,pins =
1677 <0 RK_PC1 2 &pcfg_pull_down>;
1678 };
1679 };
1680
1681 pwm6 {
1682 pwm6_pin: pwm6-pin {
1683 rockchip,pins =
1684 <0 RK_PC2 2 &pcfg_pull_none>;
1685 };
1686
1687 pwm6_pin_pull_down: pwm6-pin-pull-down {
1688 rockchip,pins =
1689 <0 RK_PC2 2 &pcfg_pull_down>;
1690 };
1691 };
1692
1693 pwm7 {
1694 pwm7_pin: pwm7-pin {
1695 rockchip,pins =
1696 <2 RK_PB0 2 &pcfg_pull_none>;
1697 };
1698
1699 pwm7_pin_pull_down: pwm7-pin-pull-down {
1700 rockchip,pins =
1701 <2 RK_PB0 2 &pcfg_pull_down>;
1702 };
1703 };
1704
1705 pwm8 {
1706 pwm8_pin: pwm8-pin {
1707 rockchip,pins =
1708 <2 RK_PB2 2 &pcfg_pull_none>;
1709 };
1710
1711 pwm8_pin_pull_down: pwm8-pin-pull-down {
1712 rockchip,pins =
1713 <2 RK_PB2 2 &pcfg_pull_down>;
1714 };
1715 };
1716
1717 pwm9 {
1718 pwm9_pin: pwm9-pin {
1719 rockchip,pins =
1720 <2 RK_PB3 2 &pcfg_pull_none>;
1721 };
1722
1723 pwm9_pin_pull_down: pwm9-pin-pull-down {
1724 rockchip,pins =
1725 <2 RK_PB3 2 &pcfg_pull_down>;
1726 };
1727 };
1728
1729 pwm10 {
1730 pwm10_pin: pwm10-pin {
1731 rockchip,pins =
1732 <2 RK_PB4 2 &pcfg_pull_none>;
1733 };
1734
1735 pwm10_pin_pull_down: pwm10-pin-pull-down {
1736 rockchip,pins =
1737 <2 RK_PB4 2 &pcfg_pull_down>;
1738 };
1739 };
1740
1741 pwm11 {
1742 pwm11_pin: pwm11-pin {
1743 rockchip,pins =
1744 <2 RK_PC0 4 &pcfg_pull_none>;
1745 };
1746
1747 pwm11_pin_pull_down: pwm11-pin-pull-down {
1748 rockchip,pins =
1749 <2 RK_PC0 4 &pcfg_pull_down>;
1750 };
1751 };
1752
1753 gmac {
1754 rmii_pins: rmii-pins {
1755 rockchip,pins =
1756 /* mac_txen */
1757 <1 RK_PC1 3 &pcfg_pull_none_12ma>,
1758 /* mac_txd1 */
1759 <1 RK_PC3 3 &pcfg_pull_none_12ma>,
1760 /* mac_txd0 */
1761 <1 RK_PC2 3 &pcfg_pull_none_12ma>,
1762 /* mac_rxd0 */
1763 <1 RK_PC4 3 &pcfg_pull_none>,
1764 /* mac_rxd1 */
1765 <1 RK_PC5 3 &pcfg_pull_none>,
1766 /* mac_rxer */
1767 <1 RK_PB7 3 &pcfg_pull_none>,
1768 /* mac_rxdv */
1769 <1 RK_PC0 3 &pcfg_pull_none>,
1770 /* mac_mdio */
1771 <1 RK_PB6 3 &pcfg_pull_none>,
1772 /* mac_mdc */
1773 <1 RK_PB5 3 &pcfg_pull_none>;
1774 };
1775
1776 mac_refclk_12ma: mac-refclk-12ma {
1777 rockchip,pins =
1778 <1 RK_PB4 3 &pcfg_pull_none_12ma>;
1779 };
1780
1781 mac_refclk: mac-refclk {
1782 rockchip,pins =
1783 <1 RK_PB4 3 &pcfg_pull_none>;
1784 };
1785 };
1786
1787 gmac-m1 {
1788 rmiim1_pins: rmiim1-pins {
1789 rockchip,pins =
1790 /* mac_txen */
1791 <4 RK_PB7 2 &pcfg_pull_none_12ma>,
1792 /* mac_txd1 */
1793 <4 RK_PA5 2 &pcfg_pull_none_12ma>,
1794 /* mac_txd0 */
1795 <4 RK_PA4 2 &pcfg_pull_none_12ma>,
1796 /* mac_rxd0 */
1797 <4 RK_PA2 2 &pcfg_pull_none>,
1798 /* mac_rxd1 */
1799 <4 RK_PA3 2 &pcfg_pull_none>,
1800 /* mac_rxer */
1801 <4 RK_PA0 2 &pcfg_pull_none>,
1802 /* mac_rxdv */
1803 <4 RK_PA1 2 &pcfg_pull_none>,
1804 /* mac_mdio */
1805 <4 RK_PB6 2 &pcfg_pull_none>,
1806 /* mac_mdc */
1807 <4 RK_PB5 2 &pcfg_pull_none>;
1808 };
1809
1810 macm1_refclk_12ma: macm1-refclk-12ma {
1811 rockchip,pins =
1812 <4 RK_PB4 2 &pcfg_pull_none_12ma>;
1813 };
1814
1815 macm1_refclk: macm1-refclk {
1816 rockchip,pins =
1817 <4 RK_PB4 2 &pcfg_pull_none>;
1818 };
1819 };
1820
1821 rtc {
1822 rtc_32k: rtc-32k {
1823 rockchip,pins =
1824 <0 RK_PC3 1 &pcfg_pull_none>;
1825 };
1826 };
1827
1828 };
1829};