| Tom Rini | 53633a8 | 2024-02-29 12:33:36 -0500 | [diff] [blame] | 1 | # SPDX-License-Identifier: GPL-2.0 |
| 2 | %YAML 1.2 |
| 3 | --- |
| 4 | $id: http://devicetree.org/schemas/serial/sifive-serial.yaml# |
| 5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | |
| 7 | title: SiFive asynchronous serial interface (UART) |
| 8 | |
| 9 | maintainers: |
| 10 | - Pragnesh Patel <pragnesh.patel@sifive.com> |
| 11 | - Paul Walmsley <paul.walmsley@sifive.com> |
| 12 | - Palmer Dabbelt <palmer@sifive.com> |
| 13 | |
| 14 | allOf: |
| 15 | - $ref: serial.yaml# |
| 16 | |
| 17 | properties: |
| 18 | compatible: |
| 19 | items: |
| 20 | - enum: |
| 21 | - sifive,fu540-c000-uart |
| 22 | - sifive,fu740-c000-uart |
| 23 | - canaan,k210-uarths |
| 24 | - const: sifive,uart0 |
| 25 | |
| 26 | description: |
| 27 | Should be something similar to "sifive,<chip>-uart" |
| 28 | for the UART as integrated on a particular chip, |
| 29 | and "sifive,uart<version>" for the general UART IP |
| 30 | block programming model. |
| 31 | |
| 32 | UART HDL that corresponds to the IP block version |
| 33 | numbers can be found here - |
| 34 | |
| 35 | https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/uart |
| 36 | |
| 37 | reg: |
| 38 | maxItems: 1 |
| 39 | |
| 40 | interrupts: |
| 41 | maxItems: 1 |
| 42 | |
| 43 | clocks: |
| 44 | maxItems: 1 |
| 45 | |
| 46 | required: |
| 47 | - compatible |
| 48 | - reg |
| 49 | - interrupts |
| 50 | - clocks |
| 51 | |
| 52 | unevaluatedProperties: false |
| 53 | |
| 54 | examples: |
| 55 | - | |
| 56 | #include <dt-bindings/clock/sifive-fu540-prci.h> |
| 57 | serial@10010000 { |
| 58 | compatible = "sifive,fu540-c000-uart", "sifive,uart0"; |
| 59 | interrupt-parent = <&plic0>; |
| 60 | interrupts = <80>; |
| 61 | reg = <0x10010000 0x1000>; |
| 62 | clocks = <&prci FU540_PRCI_CLK_TLCLK>; |
| 63 | }; |
| 64 | |
| 65 | ... |