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git01.mediatek.com / filogic / uboot / 1563250e7bc8a0dcf531a6bc750486542e2d1877 / . / dts / upstream / Bindings / serial / samsung_uart.yaml
blob: 0f0131026911cd0e07071cf38f0e9b41de9a7237 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/serial/samsung_uart.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung S3C, S5P, Exynos, and S5L (Apple SoC) SoC UART Controller
8
9maintainers:
10 - Krzysztof Kozlowski <krzk@kernel.org>
11 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
12
13description: |+
14 Each Samsung UART should have an alias correctly numbered in the "aliases"
15 node, according to serialN format, where N is the port number (non-negative
16 decimal integer) as specified by User's Manual of respective SoC.
17
18properties:
19 compatible:
20 oneOf:
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]21 - enum:
22 - apple,s5l-uart
23 - axis,artpec8-uart
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]24 - google,gs101-uart
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]25 - samsung,s3c6400-uart
26 - samsung,s5pv210-uart
27 - samsung,exynos4210-uart
28 - samsung,exynos5433-uart
29 - samsung,exynos850-uart
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]30 - items:
31 - enum:
32 - samsung,exynos7-uart
33 - tesla,fsd-uart
34 - const: samsung,exynos4210-uart
35 - items:
36 - enum:
37 - samsung,exynos7885-uart
38 - const: samsung,exynos5433-uart
39 - items:
40 - enum:
41 - samsung,exynosautov9-uart
42 - samsung,exynosautov920-uart
43 - const: samsung,exynos850-uart
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]44
45 reg:
46 maxItems: 1
47
48 reg-io-width:
49 description: |
50 The size (in bytes) of the IO accesses that should be performed
51 on the device.
52 enum: [ 1, 4 ]
53
54 clocks:
55 minItems: 2
56 maxItems: 5
57
58 clock-names:
59 description: N = 0 is allowed for SoCs without internal baud clock mux.
60 minItems: 2
61 items:
62 - const: uart
63 - pattern: '^clk_uart_baud[0-3]$'
64 - pattern: '^clk_uart_baud[0-3]$'
65 - pattern: '^clk_uart_baud[0-3]$'
66 - pattern: '^clk_uart_baud[0-3]$'
67
68 dmas:
69 items:
70 - description: DMA controller phandle and request line for RX
71 - description: DMA controller phandle and request line for TX
72
73 dma-names:
74 items:
75 - const: rx
76 - const: tx
77
78 interrupts:
79 description: RX interrupt and optionally TX interrupt.
80 minItems: 1
81 maxItems: 2
82
83 power-domains:
84 maxItems: 1
85
86 samsung,uart-fifosize:
87 description: The fifo size supported by the UART channel.
88 $ref: /schemas/types.yaml#/definitions/uint32
89 enum: [16, 64, 256]
90
91required:
92 - compatible
93 - clocks
94 - clock-names
95 - interrupts
96 - reg
97
98allOf:
99 - $ref: serial.yaml#
100
101 - if:
102 properties:
103 compatible:
104 contains:
105 enum:
106 - samsung,s5pv210-uart
107 then:
108 properties:
109 clocks:
110 minItems: 2
111 maxItems: 3
112 clock-names:
113 minItems: 2
114 items:
115 - const: uart
116 - pattern: '^clk_uart_baud[0-1]$'
117 - pattern: '^clk_uart_baud[0-1]$'
118
119 - if:
120 properties:
121 compatible:
122 contains:
123 enum:
124 - apple,s5l-uart
125 - axis,artpec8-uart
126 - samsung,exynos4210-uart
127 - samsung,exynos5433-uart
128 then:
129 properties:
130 clocks:
131 maxItems: 2
132 clock-names:
133 items:
134 - const: uart
135 - const: clk_uart_baud0
136
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]137 - if:
138 properties:
139 compatible:
140 contains:
141 enum:
142 - google,gs101-uart
143 then:
144 required:
145 - samsung,uart-fifosize
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]146 properties:
147 reg-io-width: false
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]148
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]149unevaluatedProperties: false
150
151examples:
152 - |
153 #include <dt-bindings/clock/samsung,s3c64xx-clock.h>
154
155 uart0: serial@7f005000 {
156 compatible = "samsung,s3c6400-uart";
157 reg = <0x7f005000 0x100>;
158 interrupt-parent = <&vic1>;
159 interrupts = <5>;
160 clock-names = "uart", "clk_uart_baud2",
161 "clk_uart_baud3";
162 clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>,
163 <&clocks SCLK_UART>;
164 samsung,uart-fifosize = <16>;
165 };