blob: abae658c0ed959bf05c752967da76446d8562de4 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -05001# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8998.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Global Clock & Reset Controller on MSM8998
8
9maintainers:
10 - Stephen Boyd <sboyd@kernel.org>
11 - Taniya Das <quic_tdas@quicinc.com>
12
13description: |
14 Qualcomm global clock control module provides the clocks, resets and power
15 domains on MSM8998.
16
17 See also:: include/dt-bindings/clock/qcom,gcc-msm8998.h
18
19properties:
20 compatible:
21 const: qcom,gcc-msm8998
22
23 clocks:
24 items:
25 - description: Board XO source
26 - description: Sleep clock source
27 - description: Audio reference clock (Optional clock)
28 minItems: 2
29
30 clock-names:
31 items:
32 - const: xo
33 - const: sleep_clk
34 - const: aud_ref_clk # Optional clock
35 minItems: 2
36
37required:
38 - compatible
39 - clocks
40 - clock-names
Tom Rini6b642ac2024-10-01 12:20:28 -060041 - '#power-domain-cells'
Tom Rini53633a82024-02-29 12:33:36 -050042
43allOf:
44 - $ref: qcom,gcc.yaml#
45
46unevaluatedProperties: false
47
48examples:
49 - |
50 #include <dt-bindings/clock/qcom,rpmcc.h>
51 clock-controller@100000 {
52 compatible = "qcom,gcc-msm8998";
53 #clock-cells = <1>;
54 #reset-cells = <1>;
55 #power-domain-cells = <1>;
56 reg = <0x00100000 0xb0000>;
57 clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
58 <&sleep>,
59 <0>;
60 clock-names = "xo",
61 "sleep_clk",
62 "aud_ref_clk";
63 };
64...