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git01.mediatek.com / filogic / uboot / 154e8375002dccac39b73bbb0cf7a8088b23a95b / . / arch / arm / dts / am335x-evmsk.dts
blob: b14bf2ff1b3018c2988608650c79be00c41b02bc [file] [log] [blame]
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530[diff] [blame]1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9/*
10 * AM335x Starter Kit
11 * http://www.ti.com/tool/tmdssk3358
12 */
13
14/dts-v1/;
15
16#include "am33xx.dtsi"
17#include <dt-bindings/pwm/pwm.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21 model = "TI AM335x EVM-SK";
22 compatible = "ti,am335x-evmsk", "ti,am33xx";
23
24 chosen {
25 stdout-path = &uart0;
26 tick-timer = &timer2;
27 };
28
29 cpus {
30 cpu@0 {
31 cpu0-supply = <&vdd1_reg>;
32 };
33 };
34
35 memory {
36 device_type = "memory";
37 reg = <0x80000000 0x10000000>; /* 256 MB */
38 };
39
40 vbat: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "vbat";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 regulator-boot-on;
46 };
47
48 lis3_reg: fixedregulator@1 {
49 compatible = "regulator-fixed";
50 regulator-name = "lis3_reg";
51 regulator-boot-on;
52 };
53
54 wl12xx_vmmc: fixedregulator@2 {
55 pinctrl-names = "default";
56 pinctrl-0 = <&wl12xx_gpio>;
57 compatible = "regulator-fixed";
58 regulator-name = "vwl1271";
59 regulator-min-microvolt = <1800000>;
60 regulator-max-microvolt = <1800000>;
61 gpio = <&gpio1 29 0>;
62 startup-delay-us = <70000>;
63 enable-active-high;
64 };
65
66 vtt_fixed: fixedregulator@3 {
67 compatible = "regulator-fixed";
68 regulator-name = "vtt";
69 regulator-min-microvolt = <1500000>;
70 regulator-max-microvolt = <1500000>;
71 gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
72 regulator-always-on;
73 regulator-boot-on;
74 enable-active-high;
75 };
76
77 leds {
78 pinctrl-names = "default";
79 pinctrl-0 = <&user_leds_s0>;
80
81 compatible = "gpio-leds";
82
83 led@1 {
84 label = "evmsk:green:usr0";
85 gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
86 default-state = "off";
87 };
88
89 led@2 {
90 label = "evmsk:green:usr1";
91 gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
92 default-state = "off";
93 };
94
95 led@3 {
96 label = "evmsk:green:mmc0";
97 gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
98 linux,default-trigger = "mmc0";
99 default-state = "off";
100 };
101
102 led@4 {
103 label = "evmsk:green:heartbeat";
104 gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
105 linux,default-trigger = "heartbeat";
106 default-state = "off";
107 };
108 };
109
110 gpio_buttons: gpio_buttons@0 {
111 compatible = "gpio-keys";
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530[diff] [blame]112
113 switch@1 {
114 label = "button0";
115 linux,code = <0x100>;
116 gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
117 };
118
119 switch@2 {
120 label = "button1";
121 linux,code = <0x101>;
122 gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
123 };
124
125 switch@3 {
126 label = "button2";
127 linux,code = <0x102>;
128 gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
129 wakeup-source;
130 };
131
132 switch@4 {
133 label = "button3";
134 linux,code = <0x103>;
135 gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
136 };
137 };
138
139 backlight {
140 compatible = "pwm-backlight";
141 pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
142 brightness-levels = <0 58 61 66 75 90 125 170 255>;
143 default-brightness-level = <8>;
144 };
145
146 sound {
147 compatible = "simple-audio-card";
148 simple-audio-card,name = "AM335x-EVMSK";
149 simple-audio-card,widgets =
150 "Headphone", "Headphone Jack";
151 simple-audio-card,routing =
152 "Headphone Jack", "HPLOUT",
153 "Headphone Jack", "HPROUT";
154 simple-audio-card,format = "dsp_b";
155 simple-audio-card,bitclock-master = <&sound_master>;
156 simple-audio-card,frame-master = <&sound_master>;
157 simple-audio-card,bitclock-inversion;
158
159 simple-audio-card,cpu {
160 sound-dai = <&mcasp1>;
161 };
162
163 sound_master: simple-audio-card,codec {
164 sound-dai = <&tlv320aic3106>;
165 system-clock-frequency = <24000000>;
166 };
167 };
168
169 panel {
170 compatible = "ti,tilcdc,panel";
171 pinctrl-names = "default", "sleep";
172 pinctrl-0 = <&lcd_pins_default>;
173 pinctrl-1 = <&lcd_pins_sleep>;
174 status = "okay";
175 panel-info {
176 ac-bias = <255>;
177 ac-bias-intrpt = <0>;
178 dma-burst-sz = <16>;
179 bpp = <32>;
180 fdd = <0x80>;
181 sync-edge = <0>;
182 sync-ctrl = <1>;
183 raster-order = <0>;
184 fifo-th = <0>;
185 };
186 display-timings {
187 480x272 {
188 hactive = <480>;
189 vactive = <272>;
190 hback-porch = <43>;
191 hfront-porch = <8>;
192 hsync-len = <4>;
193 vback-porch = <12>;
194 vfront-porch = <4>;
195 vsync-len = <10>;
196 clock-frequency = <9000000>;
197 hsync-active = <0>;
198 vsync-active = <0>;
199 };
200 };
201 };
202};
203
204&am33xx_pinmux {
205 pinctrl-names = "default";
206 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
207
208 lcd_pins_default: lcd_pins_default {
209 pinctrl-single,pins = <
210 AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
211 AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
212 AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
213 AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
214 AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
215 AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
216 AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
217 AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
218 AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
219 AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
220 AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
221 AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
222 AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
223 AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
224 AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
225 AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
226 AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
227 AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
228 AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
229 AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
230 AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
231 AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
232 AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
233 AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
234 AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
235 AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
236 AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
237 AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
238 >;
239 };
240
241 lcd_pins_sleep: lcd_pins_sleep {
242 pinctrl-single,pins = <
243 AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
244 AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
245 AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
246 AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
247 AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
248 AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
249 AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
250 AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
251 AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
252 AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
253 AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
254 AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
255 AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
256 AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
257 AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
258 AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
259 AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
260 AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
261 AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
262 AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
263 AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
264 AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
265 AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
266 AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
267 AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
268 AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
269 AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
270 AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
271 >;
272 };
273
274
275 user_leds_s0: user_leds_s0 {
276 pinctrl-single,pins = <
277 AM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
278 AM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
279 AM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
280 AM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
281 >;
282 };
283
284 gpio_keys_s0: gpio_keys_s0 {
285 pinctrl-single,pins = <
286 AM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
287 AM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
288 AM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
289 AM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
290 >;
291 };
292
293 i2c0_pins: pinmux_i2c0_pins {
294 pinctrl-single,pins = <
295 AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
296 AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
297 >;
298 };
299
300 uart0_pins: pinmux_uart0_pins {
301 pinctrl-single,pins = <
302 AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
303 AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
304 >;
305 };
306
307 clkout2_pin: pinmux_clkout2_pin {
308 pinctrl-single,pins = <
309 AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
310 >;
311 };
312
313 ecap2_pins: backlight_pins {
314 pinctrl-single,pins = <
315 AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */
316 >;
317 };
318
319 cpsw_default: cpsw_default {
320 pinctrl-single,pins = <
321 /* Slave 1 */
322 AM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
323 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
324 AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
325 AM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
326 AM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
327 AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
328 AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
329 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
330 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
331 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
332 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
333 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
334
335 /* Slave 2 */
336 AM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
337 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
338 AM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
339 AM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
340 AM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
341 AM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
342 AM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
343 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
344 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
345 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
346 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
347 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
348 >;
349 };
350
351 cpsw_sleep: cpsw_sleep {
352 pinctrl-single,pins = <
353 /* Slave 1 reset value */
354 AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)
355 AM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)
356 AM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)
357 AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)
358 AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)
359 AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)
360 AM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)
361 AM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)
362 AM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)
363 AM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)
364 AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)
365 AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)
366
367 /* Slave 2 reset value*/
368 AM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)
369 AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)
370 AM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)
371 AM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)
372 AM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)
373 AM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)
374 AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)
375 AM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)
376 AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)
377 AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)
378 AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)
379 AM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)
380 >;
381 };
382
383 davinci_mdio_default: davinci_mdio_default {
384 pinctrl-single,pins = <
385 /* MDIO */
386 AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
387 AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
388 >;
389 };
390
391 davinci_mdio_sleep: davinci_mdio_sleep {
392 pinctrl-single,pins = <
393 /* MDIO reset value */
394 AM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)
395 AM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)
396 >;
397 };
398
399 mmc1_pins: pinmux_mmc1_pins {
400 pinctrl-single,pins = <
401 AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
402 >;
403 };
404
405 mcasp1_pins: mcasp1_pins {
406 pinctrl-single,pins = <
407 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
408 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
409 AM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
410 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
411 >;
412 };
413
414 mcasp1_pins_sleep: mcasp1_pins_sleep {
415 pinctrl-single,pins = <
416 AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)
417 AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)
418 AM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)
419 AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)
420 >;
421 };
422
423 mmc2_pins: pinmux_mmc2_pins {
424 pinctrl-single,pins = <
425 AM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
426 AM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
427 AM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
428 AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
429 AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
430 AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
431 AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
432 >;
433 };
434
435 wl12xx_gpio: pinmux_wl12xx_gpio {
436 pinctrl-single,pins = <
437 AM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
438 >;
439 };
440};
441
442&uart0 {
443 pinctrl-names = "default";
444 pinctrl-0 = <&uart0_pins>;
445
446 status = "okay";
447};
448
449&i2c0 {
450 pinctrl-names = "default";
451 pinctrl-0 = <&i2c0_pins>;
452
453 status = "okay";
454 clock-frequency = <400000>;
455
456 tps: tps@2d {
457 reg = <0x2d>;
458 };
459
460 lis331dlh: lis331dlh@18 {
461 compatible = "st,lis331dlh", "st,lis3lv02d";
462 reg = <0x18>;
463 Vdd-supply = <&lis3_reg>;
464 Vdd_IO-supply = <&lis3_reg>;
465
466 st,click-single-x;
467 st,click-single-y;
468 st,click-single-z;
469 st,click-thresh-x = <10>;
470 st,click-thresh-y = <10>;
471 st,click-thresh-z = <10>;
472 st,irq1-click;
473 st,irq2-click;
474 st,wakeup-x-lo;
475 st,wakeup-x-hi;
476 st,wakeup-y-lo;
477 st,wakeup-y-hi;
478 st,wakeup-z-lo;
479 st,wakeup-z-hi;
480 st,min-limit-x = <120>;
481 st,min-limit-y = <120>;
482 st,min-limit-z = <140>;
483 st,max-limit-x = <550>;
484 st,max-limit-y = <550>;
485 st,max-limit-z = <750>;
486 };
487
488 tlv320aic3106: tlv320aic3106@1b {
489 #sound-dai-cells = <0>;
490 compatible = "ti,tlv320aic3106";
491 reg = <0x1b>;
492 status = "okay";
493
494 /* Regulators */
495 AVDD-supply = <&vaux2_reg>;
496 IOVDD-supply = <&vaux2_reg>;
497 DRVDD-supply = <&vaux2_reg>;
498 DVDD-supply = <&vbat>;
499 };
500};
501
502&usb {
503 status = "okay";
504};
505
506&usb_ctrl_mod {
507 status = "okay";
508};
509
510&usb0_phy {
511 status = "okay";
512};
513
514&usb1_phy {
515 status = "okay";
516};
517
518&usb0 {
519 status = "okay";
520};
521
522&usb1 {
523 status = "okay";
524 dr_mode = "host";
525};
526
527&cppi41dma {
528 status = "okay";
529};
530
531&epwmss2 {
532 status = "okay";
533
Dario Binacchi96d04d72020-12-30 00:06:30 +0100[diff] [blame]534 ecap2: ecap@100 {
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530[diff] [blame]535 status = "okay";
536 pinctrl-names = "default";
537 pinctrl-0 = <&ecap2_pins>;
538 };
539};
540
541#include "tps65910.dtsi"
542
543&tps {
544 vcc1-supply = <&vbat>;
545 vcc2-supply = <&vbat>;
546 vcc3-supply = <&vbat>;
547 vcc4-supply = <&vbat>;
548 vcc5-supply = <&vbat>;
549 vcc6-supply = <&vbat>;
550 vcc7-supply = <&vbat>;
551 vccio-supply = <&vbat>;
552
553 regulators {
554 vrtc_reg: regulator@0 {
555 regulator-always-on;
556 };
557
558 vio_reg: regulator@1 {
559 regulator-always-on;
560 };
561
562 vdd1_reg: regulator@2 {
563 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
564 regulator-name = "vdd_mpu";
565 regulator-min-microvolt = <912500>;
566 regulator-max-microvolt = <1312500>;
567 regulator-boot-on;
568 regulator-always-on;
569 };
570
571 vdd2_reg: regulator@3 {
572 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
573 regulator-name = "vdd_core";
574 regulator-min-microvolt = <912500>;
575 regulator-max-microvolt = <1150000>;
576 regulator-boot-on;
577 regulator-always-on;
578 };
579
580 vdd3_reg: regulator@4 {
581 regulator-always-on;
582 };
583
584 vdig1_reg: regulator@5 {
585 regulator-always-on;
586 };
587
588 vdig2_reg: regulator@6 {
589 regulator-always-on;
590 };
591
592 vpll_reg: regulator@7 {
593 regulator-always-on;
594 };
595
596 vdac_reg: regulator@8 {
597 regulator-always-on;
598 };
599
600 vaux1_reg: regulator@9 {
601 regulator-always-on;
602 };
603
604 vaux2_reg: regulator@10 {
605 regulator-always-on;
606 };
607
608 vaux33_reg: regulator@11 {
609 regulator-always-on;
610 };
611
612 vmmc_reg: regulator@12 {
613 regulator-min-microvolt = <1800000>;
614 regulator-max-microvolt = <3300000>;
615 regulator-always-on;
616 };
617 };
618};
619
620&mac {
621 pinctrl-names = "default", "sleep";
622 pinctrl-0 = <&cpsw_default>;
623 pinctrl-1 = <&cpsw_sleep>;
624 dual_emac = <1>;
625 status = "okay";
626};
627
628&davinci_mdio {
629 pinctrl-names = "default", "sleep";
630 pinctrl-0 = <&davinci_mdio_default>;
631 pinctrl-1 = <&davinci_mdio_sleep>;
632 status = "okay";
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]633
634 ethphy0: ethernet-phy@0 {
635 reg = <0>;
636 };
637
638 ethphy1: ethernet-phy@1 {
639 reg = <1>;
640 };
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530[diff] [blame]641};
642
643&cpsw_emac0 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]644 phy-handle = <&ethphy0>;
645 phy-mode = "rgmii-id";
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530[diff] [blame]646 dual_emac_res_vlan = <1>;
647};
648
649&cpsw_emac1 {
Grygorii Strashkoa6f37dc2019-08-31 10:30:34 +0300[diff] [blame]650 phy-handle = <&ethphy1>;
651 phy-mode = "rgmii-id";
Lokesh Vutla5a954ba2016-05-16 11:24:28 +0530[diff] [blame]652 dual_emac_res_vlan = <2>;
653};
654
655&mmc1 {
656 status = "okay";
657 vmmc-supply = <&vmmc_reg>;
658 bus-width = <4>;
659 pinctrl-names = "default";
660 pinctrl-0 = <&mmc1_pins>;
661 cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
662};
663
664&sham {
665 status = "okay";
666};
667
668&aes {
669 status = "okay";
670};
671
672&gpio0 {
673 ti,no-reset-on-init;
674};
675
676&mmc2 {
677 status = "okay";
678 vmmc-supply = <&wl12xx_vmmc>;
679 ti,non-removable;
680 bus-width = <4>;
681 cap-power-off-card;
682 pinctrl-names = "default";
683 pinctrl-0 = <&mmc2_pins>;
684
685 #address-cells = <1>;
686 #size-cells = <0>;
687 wlcore: wlcore@2 {
688 compatible = "ti,wl1271";
689 reg = <2>;
690 interrupt-parent = <&gpio0>;
691 interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; /* gpio 31 */
692 ref-clock-frequency = <38400000>;
693 };
694};
695
696&mcasp1 {
697 #sound-dai-cells = <0>;
698 pinctrl-names = "default", "sleep";
699 pinctrl-0 = <&mcasp1_pins>;
700 pinctrl-1 = <&mcasp1_pins_sleep>;
701
702 status = "okay";
703
704 op-mode = <0>; /* MCASP_IIS_MODE */
705 tdm-slots = <2>;
706 /* 4 serializers */
707 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
708 0 0 1 2
709 >;
710 tx-num-evt = <32>;
711 rx-num-evt = <32>;
712};
713
714&tscadc {
715 status = "okay";
716 tsc {
717 ti,wires = <4>;
718 ti,x-plate-resistance = <200>;
719 ti,coordinate-readouts = <5>;
720 ti,wire-config = <0x00 0x11 0x22 0x33>;
721 };
722};
723
724&lcdc {
725 status = "okay";
726};
Dario Binacchi95657952021-06-02 22:38:03 +0200[diff] [blame]727
728&rtc {
729 clocks = <&clk_32768_ck>, <&clk_24mhz_clkctrl AM3_CLK_24MHZ_CLKDIV32K_CLKCTRL 0>;
730 clock-names = "ext-clk", "int-clk";
731};