blob: 4061fa244c49f3fc854ed6fc605816b498805d5b [file] [log] [blame]
Simon Glassac4df6f2019-09-25 08:11:30 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
4 */
5
6#include <common.h>
Simon Glass1fa70f82019-11-14 12:57:34 -07007#include <cpu_func.h>
Simon Glassac4df6f2019-09-25 08:11:30 -06008#include <dm.h>
9#include <errno.h>
Simon Glass97589732020-05-10 11:40:02 -060010#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060011#include <log.h>
Simon Glassac4df6f2019-09-25 08:11:30 -060012#include <rtc.h>
Simon Glass50461092020-04-08 16:57:35 -060013#include <acpi/acpi_s3.h>
Simon Glassac4df6f2019-09-25 08:11:30 -060014#include <asm/cmos_layout.h>
15#include <asm/early_cmos.h>
16#include <asm/io.h>
17#include <asm/mrccache.h>
18#include <asm/post.h>
19#include <asm/processor.h>
20#include <asm/fsp/fsp_support.h>
21
22DECLARE_GLOBAL_DATA_PTR;
23
24int checkcpu(void)
25{
26 return 0;
27}
28
29int print_cpuinfo(void)
30{
31 post_code(POST_CPU_INFO);
32 return default_print_cpuinfo();
33}
34
35int fsp_init_phase_pci(void)
36{
37 u32 status;
38
39 /* call into FspNotify */
40 debug("Calling into FSP (notify phase INIT_PHASE_PCI): ");
41 status = fsp_notify(NULL, INIT_PHASE_PCI);
42 if (status)
43 debug("fail, error code %x\n", status);
44 else
45 debug("OK\n");
46
47 return status ? -EPERM : 0;
48}
49
Simon Glass75ece5f2020-07-16 21:22:38 -060050void board_final_init(void)
Simon Glassac4df6f2019-09-25 08:11:30 -060051{
52 u32 status;
53
54 /* call into FspNotify */
55 debug("Calling into FSP (notify phase INIT_PHASE_BOOT): ");
56 status = fsp_notify(NULL, INIT_PHASE_BOOT);
57 if (status)
58 debug("fail, error code %x\n", status);
59 else
60 debug("OK\n");
61}
62
Simon Glassad7bb302020-09-22 12:45:28 -060063void board_final_cleanup(void)
64{
65 u32 status;
66
67 /* TODO(sjg@chromium.org): This causes Linux to crash */
68 return;
69
70 /* call into FspNotify */
71 debug("Calling into FSP (notify phase INIT_PHASE_END_FIRMWARE): ");
72 status = fsp_notify(NULL, INIT_PHASE_END_FIRMWARE);
73 if (status)
74 debug("fail, error code %x\n", status);
75 else
76 debug("OK\n");
77}
78
Simon Glassac4df6f2019-09-25 08:11:30 -060079int fsp_save_s3_stack(void)
80{
81 struct udevice *dev;
82 int ret;
83
84 if (gd->arch.prev_sleep_state == ACPI_S3)
85 return 0;
86
87 ret = uclass_get_device(UCLASS_RTC, 0, &dev);
88 if (ret) {
89 debug("Cannot find RTC: err=%d\n", ret);
90 return -ENODEV;
91 }
92
93 /* Save the stack address to CMOS */
94 ret = rtc_write32(dev, CMOS_FSP_STACK_ADDR, gd->start_addr_sp);
95 if (ret) {
96 debug("Save stack address to CMOS: err=%d\n", ret);
97 return -EIO;
98 }
99
100 return 0;
101}