Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com> |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <handoff.h> |
Simon Glass | 6980b6b | 2019-11-14 12:57:45 -0700 | [diff] [blame] | 8 | #include <init.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 9 | #include <log.h> |
Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 10 | #include <asm/fsp/fsp_support.h> |
| 11 | #include <asm/e820.h> |
| 12 | #include <asm/mrccache.h> |
Simon Glass | 8ccadee | 2019-12-06 21:42:12 -0700 | [diff] [blame] | 13 | #include <asm/mtrr.h> |
Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 14 | #include <asm/post.h> |
| 15 | |
| 16 | DECLARE_GLOBAL_DATA_PTR; |
| 17 | |
| 18 | int fsp_scan_for_ram_size(void) |
| 19 | { |
| 20 | phys_size_t ram_size = 0; |
| 21 | const struct hob_header *hdr; |
| 22 | struct hob_res_desc *res_desc; |
| 23 | |
| 24 | hdr = gd->arch.hob_list; |
| 25 | while (!end_of_hob(hdr)) { |
| 26 | if (hdr->type == HOB_TYPE_RES_DESC) { |
| 27 | res_desc = (struct hob_res_desc *)hdr; |
| 28 | if (res_desc->type == RES_SYS_MEM || |
| 29 | res_desc->type == RES_MEM_RESERVED) |
| 30 | ram_size += res_desc->len; |
| 31 | } |
| 32 | hdr = get_next_hob(hdr); |
| 33 | } |
| 34 | |
| 35 | gd->ram_size = ram_size; |
| 36 | post_code(POST_DRAM); |
| 37 | |
| 38 | return 0; |
| 39 | }; |
| 40 | |
| 41 | int dram_init_banksize(void) |
| 42 | { |
Simon Glass | 75545f7 | 2019-12-06 21:42:11 -0700 | [diff] [blame] | 43 | const struct hob_header *hdr; |
| 44 | struct hob_res_desc *res_desc; |
| 45 | phys_addr_t low_end; |
| 46 | uint bank; |
| 47 | |
Simon Glass | d89c4a3 | 2020-04-26 09:12:53 -0600 | [diff] [blame] | 48 | if (!ll_boot_init()) { |
| 49 | gd->bd->bi_dram[0].start = 0; |
| 50 | gd->bd->bi_dram[0].size = gd->ram_size; |
| 51 | |
| 52 | mtrr_add_request(MTRR_TYPE_WRBACK, 0, gd->ram_size); |
| 53 | return 0; |
| 54 | } |
| 55 | |
Simon Glass | 75545f7 | 2019-12-06 21:42:11 -0700 | [diff] [blame] | 56 | low_end = 0; |
| 57 | for (bank = 1, hdr = gd->arch.hob_list; |
| 58 | bank < CONFIG_NR_DRAM_BANKS && !end_of_hob(hdr); |
| 59 | hdr = get_next_hob(hdr)) { |
| 60 | if (hdr->type != HOB_TYPE_RES_DESC) |
| 61 | continue; |
| 62 | res_desc = (struct hob_res_desc *)hdr; |
| 63 | if (res_desc->type != RES_SYS_MEM && |
| 64 | res_desc->type != RES_MEM_RESERVED) |
| 65 | continue; |
| 66 | if (res_desc->phys_start < (1ULL << 32)) { |
| 67 | low_end = max(low_end, |
| 68 | res_desc->phys_start + res_desc->len); |
| 69 | continue; |
| 70 | } |
| 71 | |
| 72 | gd->bd->bi_dram[bank].start = res_desc->phys_start; |
| 73 | gd->bd->bi_dram[bank].size = res_desc->len; |
Simon Glass | 8ccadee | 2019-12-06 21:42:12 -0700 | [diff] [blame] | 74 | mtrr_add_request(MTRR_TYPE_WRBACK, res_desc->phys_start, |
| 75 | res_desc->len); |
Simon Glass | 75545f7 | 2019-12-06 21:42:11 -0700 | [diff] [blame] | 76 | log_debug("ram %llx %llx\n", gd->bd->bi_dram[bank].start, |
| 77 | gd->bd->bi_dram[bank].size); |
| 78 | } |
| 79 | |
| 80 | /* Add the memory below 4GB */ |
Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 81 | gd->bd->bi_dram[0].start = 0; |
Simon Glass | 75545f7 | 2019-12-06 21:42:11 -0700 | [diff] [blame] | 82 | gd->bd->bi_dram[0].size = low_end; |
Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 83 | |
Simon Glass | 8ccadee | 2019-12-06 21:42:12 -0700 | [diff] [blame] | 84 | mtrr_add_request(MTRR_TYPE_WRBACK, 0, low_end); |
| 85 | |
Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 86 | return 0; |
| 87 | } |
| 88 | |
| 89 | unsigned int install_e820_map(unsigned int max_entries, |
| 90 | struct e820_entry *entries) |
| 91 | { |
| 92 | unsigned int num_entries = 0; |
| 93 | const struct hob_header *hdr; |
| 94 | struct hob_res_desc *res_desc; |
| 95 | |
| 96 | hdr = gd->arch.hob_list; |
| 97 | |
| 98 | while (!end_of_hob(hdr)) { |
| 99 | if (hdr->type == HOB_TYPE_RES_DESC) { |
| 100 | res_desc = (struct hob_res_desc *)hdr; |
| 101 | entries[num_entries].addr = res_desc->phys_start; |
| 102 | entries[num_entries].size = res_desc->len; |
| 103 | |
| 104 | if (res_desc->type == RES_SYS_MEM) |
| 105 | entries[num_entries].type = E820_RAM; |
| 106 | else if (res_desc->type == RES_MEM_RESERVED) |
| 107 | entries[num_entries].type = E820_RESERVED; |
| 108 | |
| 109 | num_entries++; |
| 110 | } |
| 111 | hdr = get_next_hob(hdr); |
| 112 | } |
| 113 | |
| 114 | /* Mark PCIe ECAM address range as reserved */ |
| 115 | entries[num_entries].addr = CONFIG_PCIE_ECAM_BASE; |
| 116 | entries[num_entries].size = CONFIG_PCIE_ECAM_SIZE; |
| 117 | entries[num_entries].type = E820_RESERVED; |
| 118 | num_entries++; |
| 119 | |
Simon Glass | e6ad202 | 2020-07-09 18:43:16 -0600 | [diff] [blame] | 120 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { |
| 121 | ulong stack_size; |
| 122 | |
| 123 | stack_size = CONFIG_IS_ENABLED(HAVE_ACPI_RESUME, |
Heinrich Schuchardt | 99186b3 | 2020-07-29 12:31:17 +0200 | [diff] [blame] | 124 | (CONFIG_STACK_SIZE_RESUME), (0)); |
Simon Glass | e6ad202 | 2020-07-09 18:43:16 -0600 | [diff] [blame] | 125 | /* |
| 126 | * Everything between U-Boot's stack and ram top needs to be |
| 127 | * reserved in order for ACPI S3 resume to work. |
| 128 | */ |
| 129 | entries[num_entries].addr = gd->start_addr_sp - stack_size; |
| 130 | entries[num_entries].size = gd->ram_top - gd->start_addr_sp + |
| 131 | stack_size; |
| 132 | entries[num_entries].type = E820_RESERVED; |
| 133 | num_entries++; |
| 134 | } |
Simon Glass | ddb39b2 | 2019-08-24 14:10:32 -0600 | [diff] [blame] | 135 | |
| 136 | return num_entries; |
| 137 | } |
Simon Glass | 2562808 | 2019-09-25 08:11:41 -0600 | [diff] [blame] | 138 | |
| 139 | #if CONFIG_IS_ENABLED(HANDOFF) && IS_ENABLED(CONFIG_USE_HOB) |
| 140 | int handoff_arch_save(struct spl_handoff *ho) |
| 141 | { |
| 142 | ho->arch.usable_ram_top = fsp_get_usable_lowmem_top(gd->arch.hob_list); |
| 143 | ho->arch.hob_list = gd->arch.hob_list; |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | #endif |