Paul Burton | 96c6847 | 2018-12-16 19:25:22 -0300 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * JZ4780 common routines |
| 4 | * |
| 5 | * Copyright (c) 2013 Imagination Technologies |
| 6 | * Author: Paul Burton <paul.burton@imgtec.com> |
| 7 | */ |
| 8 | |
| 9 | #include <config.h> |
Paul Burton | 96c6847 | 2018-12-16 19:25:22 -0300 | [diff] [blame] | 10 | #include <asm/io.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 11 | #include <linux/bitops.h> |
Paul Burton | 96c6847 | 2018-12-16 19:25:22 -0300 | [diff] [blame] | 12 | #include <mach/jz4780.h> |
| 13 | |
| 14 | /* WDT */ |
| 15 | #define WDT_TDR 0x00 |
| 16 | #define WDT_TCER 0x04 |
| 17 | #define WDT_TCNT 0x08 |
| 18 | #define WDT_TCSR 0x0C |
| 19 | |
| 20 | /* Register definition */ |
| 21 | #define WDT_TCSR_PRESCALE_BIT 3 |
| 22 | #define WDT_TCSR_PRESCALE_MASK (0x7 << WDT_TCSR_PRESCALE_BIT) |
| 23 | #define WDT_TCSR_PRESCALE1 (0x0 << WDT_TCSR_PRESCALE_BIT) |
| 24 | #define WDT_TCSR_PRESCALE4 (0x1 << WDT_TCSR_PRESCALE_BIT) |
| 25 | #define WDT_TCSR_PRESCALE16 (0x2 << WDT_TCSR_PRESCALE_BIT) |
| 26 | #define WDT_TCSR_PRESCALE64 (0x3 << WDT_TCSR_PRESCALE_BIT) |
| 27 | #define WDT_TCSR_PRESCALE256 (0x4 << WDT_TCSR_PRESCALE_BIT) |
| 28 | #define WDT_TCSR_PRESCALE1024 (0x5 << WDT_TCSR_PRESCALE_BIT) |
| 29 | #define WDT_TCSR_EXT_EN BIT(2) |
| 30 | #define WDT_TCSR_RTC_EN BIT(1) |
| 31 | #define WDT_TCSR_PCK_EN BIT(0) |
| 32 | |
| 33 | #define WDT_TCER_TCEN BIT(0) |
| 34 | |
| 35 | void _machine_restart(void) |
| 36 | { |
| 37 | void __iomem *wdt_regs = (void __iomem *)WDT_BASE; |
| 38 | |
| 39 | /* EXTAL as the timer clock input. */ |
| 40 | writew(WDT_TCSR_PRESCALE1 | WDT_TCSR_EXT_EN, wdt_regs + WDT_TCSR); |
| 41 | |
| 42 | /* Reset the WDT counter and timeout. */ |
| 43 | writew(0, wdt_regs + WDT_TCNT); |
| 44 | writew(0, wdt_regs + WDT_TDR); |
| 45 | |
| 46 | jz4780_tcu_wdt_start(); |
| 47 | |
| 48 | /* WDT start */ |
| 49 | writeb(WDT_TCER_TCEN, wdt_regs + WDT_TCER); |
| 50 | |
| 51 | for (;;) |
| 52 | ; |
| 53 | } |