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git01.mediatek.com / filogic / uboot / 154bdbf3e99416aab881b3aea89fcb560b305f16 / . / arch / arm / dts / imx6ul-opos6uldev-u-boot.dtsi
blob: 3b52d6bbd9b9fa69226fff36ae0c32298b88f0f2 [file] [log] [blame]
Sébastien Szymanski6d1193d2018-09-06 09:51:53 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source extras for U-Boot for the OPOS6ULDev board
4 *
5 * Copyright (C) 2018 Armadeus Systems <support@armadeus.com>
6 */
7
8#include "imx6ul-opos6ul-u-boot.dtsi"
9
10&aips1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]11 bootph-pre-ram;
Sébastien Szymanski6d1193d2018-09-06 09:51:53 +0200[diff] [blame]12
13 spba-bus@02000000 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]14 bootph-pre-ram;
Sébastien Szymanski6d1193d2018-09-06 09:51:53 +0200[diff] [blame]15 };
16};
17
Sébastien Szymanskid5c96132019-10-21 15:33:03 +0200[diff] [blame]18&lcdif {
Sébastien Szymanski0ab32842024-02-27 16:40:01 +0100[diff] [blame]19 display = <&display0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-some-ram;
Sébastien Szymanski0ab32842024-02-27 16:40:01 +0100[diff] [blame]21
22 display0: display0 {
23 bits-per-pixel = <18>;
24 bus-width = <18>;
25
26 display-timings {
27 timing0 {
28 clock-frequency = <33300000>;
29 hactive = <800>;
30 vactive = <480>;
31 hback-porch = <36>;
32 hfront-porch = <210>;
33 vback-porch = <13>;
34 vfront-porch = <22>;
35 hsync-len = <10>;
36 vsync-len = <10>;
37 de-active = <1>;
38 pixelclk-active = <0>;
39 };
40 };
41 };
Sébastien Szymanskid5c96132019-10-21 15:33:03 +0200[diff] [blame]42};
43
Sébastien Szymanski6d1193d2018-09-06 09:51:53 +0200[diff] [blame]44&pinctrl_uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-pre-ram;
Sébastien Szymanski6d1193d2018-09-06 09:51:53 +0200[diff] [blame]46};
47
48&uart1 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-pre-ram;
Sébastien Szymanski6d1193d2018-09-06 09:51:53 +0200[diff] [blame]50};