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git01.mediatek.com / filogic / uboot / 1536f25a2da30713d6848d423054cd0ac80c41bf / . / arch / m68k / cpu / mcf523x / start.S
blob: 4c9c96d7831e4e88a4237a38f1b7cdf0fda91b62 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: GPL-2.0+ */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]2/*
3 * Copyright (C) 2003 Josef Baumgartner <josef.baumgartner@telex.de>
4 * Based on code from Bernhard Kuhn <bkuhn@metrowerks.com>
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]5 */
6
Wolfgang Denk0191e472010-10-26 14:34:52 +0200[diff] [blame]7#include <asm-offsets.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]8#include <config.h>
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600[diff] [blame]9#include <asm/cache.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]10
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]11#define _START _start
12#define _FAULT _fault
13
14#define SAVE_ALL \
15 move.w #0x2700,%sr; /* disable intrs */ \
16 subl #60,%sp; /* space for 15 regs */ \
17 moveml %d0-%d7/%a0-%a6,%sp@;
18
19#define RESTORE_ALL \
20 moveml %sp@,%d0-%d7/%a0-%a6; \
21 addl #60,%sp; /* space for 15 regs */ \
22 rte;
23
24.text
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]25
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]26/*
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]27 * Vector table. This is used for initial platform startup.
28 * These vectors are to catch any un-intended traps.
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]29 */
30_vectors:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]31INITSP: .long 0x00000000 /* Initial SP */
32INITPC: .long _START /* Initial PC */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]33
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]34vector02_0F:
35.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
36.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]37
38/* Reserved */
39vector10_17:
40.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
41
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]42vector18_1F:
43.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]44
45/* TRAP #0 - #15 */
46vector20_2F:
47.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
48.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
49
50/* Reserved */
51vector30_3F:
52.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
53.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
54
55vector64_127:
56.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
57.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
58.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
59.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
60.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
61.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
62.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
63.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
64
65vector128_191:
66.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
67.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
68.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
69.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
70.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
71.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
72.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
73.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
74
75vector192_255:
76.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
77.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
78.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
79.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
80.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
81.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
82.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
83.long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT
84
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]85.text
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]86
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]87.globl _start
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]88_start:
89 nop
90 nop
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]91 move.w #0x2700,%sr /* Mask off Interrupt */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]92
93 /* Set vector base register at the beginning of the Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]94 move.l #CONFIG_SYS_FLASH_BASE, %d0
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]95 movec %d0, %VBR
96
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]97 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_CTRL), %d0
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]98 movec %d0, %RAMBAR1
99
100 /* invalidate and disable cache */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]101 move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */
102 movec %d0, %CACR /* Invalidate cache */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]103 nop
104 move.l #0, %d0
105 movec %d0, %ACR0
106 movec %d0, %ACR1
107
108 /* initialize general use internal ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]109 move.l #0, %d0
110 move.l #(ICACHE_STATUS), %a1 /* icache */
111 move.l #(DCACHE_STATUS), %a2 /* icache */
112 move.l %d0, (%a1)
113 move.l %d0, (%a2)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]114
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]115 /* put relocation table address to a5 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]116 move.l #__got_start, %a5
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]117
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]118 /* setup stack initially on top of internal static ram */
119 move.l #(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE), %sp
120
121 /*
122 * if configured, malloc_f arena will be reserved first,
123 * then (and always) gd struct space will be reserved
124 */
125 move.l %sp, -(%sp)
126 move.l #board_init_f_alloc_reserve, %a1
127 jsr (%a1)
128
129 /* update stack and frame-pointers */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]130 move.l %d0, %sp
131 move.l %sp, %fp
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]132
133 /* initialize reserved area */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]134 move.l %d0, -(%sp)
angelo@sysam.itef9707c2016-04-27 21:50:44 +0200[diff] [blame]135 move.l #board_init_f_init_reserve, %a1
136 jsr (%a1)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]137
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]138 /* run low-level CPU init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]139 move.l #cpu_init_f, %a1
140 jsr (%a1)
141
angelo@sysam.itb8cd1322016-04-12 00:30:59 +0200[diff] [blame]142 /* run low-level board init code (from flash) */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]143 clr.l %sp@-
144 move.l #board_init_f, %a1
145 jsr (%a1)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]146
147 /* board_init_f() does not return */
148
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]149/******************************************************************************/
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]150
151/*
Simon Glass284f71b2019-12-28 10:44:45 -0700[diff] [blame]152 * void relocate_code(addr_sp, gd, addr_moni)
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]153 *
154 * This "function" does not return, instead it continues in RAM
155 * after relocating the monitor code.
156 *
157 * r3 = dest
158 * r4 = src
159 * r5 = length in bytes
160 * r6 = cachelinesize
161 */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]162.globl relocate_code
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]163relocate_code:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]164 link.w %a6,#0
165 move.l 8(%a6), %sp /* set new stack pointer */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]166
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]167 move.l 12(%a6), %d0 /* Save copy of Global Data pointer */
168 move.l 16(%a6), %a0 /* Save copy of Destination Address */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]169
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]170 move.l #CONFIG_SYS_MONITOR_BASE, %a1
171 move.l #__init_end, %a2
172 move.l %a0, %a3
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]173
174 /* copy the code to RAM */
1751:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]176 move.l (%a1)+, (%a3)+
177 cmp.l %a1,%a2
178 bgt.s 1b
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]179
180/*
181 * We are done. Do not return, instead branch to second part of board
182 * initialization, now running from RAM.
183 */
184 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]185 add.l #(in_ram - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]186 jmp (%a1)
187
188in_ram:
189
190clear_bss:
191 /*
192 * Now clear BSS segment
193 */
194 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]195 add.l #(_sbss - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]196 move.l %a0, %d1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]197 add.l #(_ebss - CONFIG_SYS_MONITOR_BASE),%d1
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]1986:
199 clr.l (%a1)+
200 cmp.l %a1,%d1
201 bgt.s 6b
202
203 /*
204 * fix got table in RAM
205 */
206 move.l %a0, %a1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]207 add.l #(__got_start - CONFIG_SYS_MONITOR_BASE),%a1
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]208 move.l %a1,%a5 /* * fix got pointer register a5 */
209
210 move.l %a0, %a2
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200[diff] [blame]211 add.l #(__got_end - CONFIG_SYS_MONITOR_BASE),%a2
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]212
2137:
214 move.l (%a1),%d1
215 sub.l #_start,%d1
216 add.l %a0,%d1
217 move.l %d1,(%a1)+
218 cmp.l %a2, %a1
219 bne 7b
220
221 /* calculate relative jump to board_init_r in ram */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]222 move.l %a0, %a1
223 add.l #(board_init_r - CONFIG_SYS_MONITOR_BASE), %a1
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]224
225 /* set parameters for board_init_r */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]226 move.l %a0,-(%sp) /* dest_addr */
227 move.l %d0,-(%sp) /* gd */
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]228 jsr (%a1)
229
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]230/******************************************************************************/
231
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]232/* exception code */
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]233.globl _fault
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]234_fault:
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]235 bra _fault
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]236
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]237.globl _exc_handler
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]238_exc_handler:
239 SAVE_ALL
240 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]241 bsr exc_handler
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]242 addql #4,%sp
243 RESTORE_ALL
244
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]245.globl _int_handler
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]246_int_handler:
247 SAVE_ALL
248 movel %sp,%sp@-
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]249 bsr int_handler
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]250 addql #4,%sp
251 RESTORE_ALL
252
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]253/******************************************************************************/
TsiChungLiewb859ef12007-08-16 19:23:50 -0500[diff] [blame]254
Angelo Dureghello65d59912016-05-22 00:14:29 +0200[diff] [blame]255.align 4