| developer | d8b34fb | 2022-05-20 11:22:36 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* |
| 3 | * Copyright (C) 2022 MediaTek Inc. All rights reserved. |
| 4 | * |
| 5 | * Author: Weijie Gao <weijie.gao@mediatek.com> |
| 6 | */ |
| 7 | |
| 8 | #ifndef _DT_BINDINGS_MT7621_CLK_H_ |
| 9 | #define _DT_BINDINGS_MT7621_CLK_H_ |
| 10 | |
| 11 | #define MT7621_CLK_XTAL 0 |
| 12 | #define MT7621_CLK_CPU 1 |
| 13 | #define MT7621_CLK_BUS 2 |
| 14 | #define MT7621_CLK_50M 3 |
| 15 | #define MT7621_CLK_125M 4 |
| 16 | #define MT7621_CLK_150M 5 |
| 17 | #define MT7621_CLK_250M 6 |
| 18 | #define MT7621_CLK_270M 7 |
| 19 | |
| 20 | #define MT7621_CLK_HSDMA 8 |
| 21 | #define MT7621_CLK_FE 9 |
| 22 | #define MT7621_CLK_SP_DIVTX 10 |
| 23 | #define MT7621_CLK_TIMER 11 |
| 24 | #define MT7621_CLK_PCM 12 |
| 25 | #define MT7621_CLK_PIO 13 |
| 26 | #define MT7621_CLK_GDMA 14 |
| 27 | #define MT7621_CLK_NAND 15 |
| 28 | #define MT7621_CLK_I2C 16 |
| 29 | #define MT7621_CLK_I2S 17 |
| 30 | #define MT7621_CLK_SPI 18 |
| 31 | #define MT7621_CLK_UART1 19 |
| 32 | #define MT7621_CLK_UART2 20 |
| 33 | #define MT7621_CLK_UART3 21 |
| 34 | #define MT7621_CLK_ETH 22 |
| 35 | #define MT7621_CLK_PCIE0 23 |
| 36 | #define MT7621_CLK_PCIE1 24 |
| 37 | #define MT7621_CLK_PCIE2 25 |
| 38 | #define MT7621_CLK_CRYPTO 26 |
| 39 | #define MT7621_CLK_SHXC 27 |
| 40 | |
| 41 | #define MT7621_CLK_MAX 28 |
| 42 | |
| 43 | /* for u-boot only */ |
| 44 | #define MT7621_CLK_DDR 29 |
| 45 | |
| 46 | #endif /* _DT_BINDINGS_MT7621_CLK_H_ */ |