blob: 5ed1b8bae188a22929941175048b36c9749ec9fe [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Ian Campbell6efe3692014-05-05 11:52:26 +01002/*
3 * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
4 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
5 *
6 * (C) Copyright 2007-2011
7 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
8 * Tom Cubie <tangliang@allwinnertech.com>
9 *
10 * Some board init for the Allwinner A10-evb board.
Ian Campbell6efe3692014-05-05 11:52:26 +010011 */
12
13#include <common.h>
Jagan Teki73a3ecf2018-05-07 13:03:36 +053014#include <dm.h>
Hans de Goede63deaa82014-10-02 21:13:54 +020015#include <mmc.h>
Hans de Goeded9ee84b2015-10-03 15:18:33 +020016#include <axp_pmic.h>
Jagan Teki73a3ecf2018-05-07 13:03:36 +053017#include <generic-phy.h>
18#include <phy-sun4i-usb.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010019#include <asm/arch/clock.h>
Jonathan Liuabc1aae2014-06-14 08:59:09 +020020#include <asm/arch/cpu.h>
Luc Verhaegen4869a8c2014-08-13 07:55:07 +020021#include <asm/arch/display.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010022#include <asm/arch/dram.h>
Ian Campbellb4e9f2f2014-05-05 14:42:31 +010023#include <asm/arch/gpio.h>
24#include <asm/arch/mmc.h>
Hans de Goedea146c502016-07-09 09:56:56 +020025#include <asm/arch/spl.h>
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +020026#ifndef CONFIG_ARM64
27#include <asm/armv7.h>
28#endif
Hans de Goeded9d05652015-04-23 23:23:50 +020029#include <asm/gpio.h>
Jonathan Liuabc1aae2014-06-14 08:59:09 +020030#include <asm/io.h>
Hans de Goedee5fe5482016-07-29 11:47:03 +020031#include <crc.h>
Hans de Goedea146c502016-07-09 09:56:56 +020032#include <environment.h>
Masahiro Yamada75f82d02018-03-05 01:20:11 +090033#include <linux/libfdt.h>
Hans de Goede5ed52f62015-08-15 11:55:26 +020034#include <nand.h>
Jonathan Liuabc1aae2014-06-14 08:59:09 +020035#include <net.h>
Maxime Ripardae56d972017-08-23 10:08:29 +020036#include <spl.h>
Jelle van der Waa3f3a3092016-02-23 18:47:19 +010037#include <sy8106a.h>
Simon Glassd9a766f2017-05-17 08:23:00 -060038#include <asm/setup.h>
Ian Campbell6efe3692014-05-05 11:52:26 +010039
Hans de Goedea5b4cfe2015-02-16 17:23:25 +010040#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
41/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
42int soft_i2c_gpio_sda;
43int soft_i2c_gpio_scl;
Hans de Goeded9d05652015-04-23 23:23:50 +020044
45static int soft_i2c_board_init(void)
46{
47 int ret;
48
49 soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
50 if (soft_i2c_gpio_sda < 0) {
51 printf("Error invalid soft i2c sda pin: '%s', err %d\n",
52 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
53 return soft_i2c_gpio_sda;
54 }
55 ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
56 if (ret) {
57 printf("Error requesting soft i2c sda pin: '%s', err %d\n",
58 CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
59 return ret;
60 }
61
62 soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
63 if (soft_i2c_gpio_scl < 0) {
64 printf("Error invalid soft i2c scl pin: '%s', err %d\n",
65 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
66 return soft_i2c_gpio_scl;
67 }
68 ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
69 if (ret) {
70 printf("Error requesting soft i2c scl pin: '%s', err %d\n",
71 CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
72 return ret;
73 }
74
75 return 0;
76}
77#else
78static int soft_i2c_board_init(void) { return 0; }
Hans de Goedea5b4cfe2015-02-16 17:23:25 +010079#endif
80
Ian Campbell6efe3692014-05-05 11:52:26 +010081DECLARE_GLOBAL_DATA_PTR;
82
Jernej Skrabec07da8802017-04-27 00:03:35 +020083void i2c_init_board(void)
84{
85#ifdef CONFIG_I2C0_ENABLE
86#if defined(CONFIG_MACH_SUN4I) || \
87 defined(CONFIG_MACH_SUN5I) || \
88 defined(CONFIG_MACH_SUN7I) || \
89 defined(CONFIG_MACH_SUN8I_R40)
90 sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
91 sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
92 clock_twi_onoff(0, 1);
93#elif defined(CONFIG_MACH_SUN6I)
94 sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
95 sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
96 clock_twi_onoff(0, 1);
97#elif defined(CONFIG_MACH_SUN8I)
98 sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
99 sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
100 clock_twi_onoff(0, 1);
101#endif
102#endif
103
104#ifdef CONFIG_I2C1_ENABLE
105#if defined(CONFIG_MACH_SUN4I) || \
106 defined(CONFIG_MACH_SUN7I) || \
107 defined(CONFIG_MACH_SUN8I_R40)
108 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
109 sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
110 clock_twi_onoff(1, 1);
111#elif defined(CONFIG_MACH_SUN5I)
112 sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
113 sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
114 clock_twi_onoff(1, 1);
115#elif defined(CONFIG_MACH_SUN6I)
116 sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
117 sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
118 clock_twi_onoff(1, 1);
119#elif defined(CONFIG_MACH_SUN8I)
120 sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
121 sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
122 clock_twi_onoff(1, 1);
123#endif
124#endif
125
126#ifdef CONFIG_I2C2_ENABLE
127#if defined(CONFIG_MACH_SUN4I) || \
128 defined(CONFIG_MACH_SUN7I) || \
129 defined(CONFIG_MACH_SUN8I_R40)
130 sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
131 sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
132 clock_twi_onoff(2, 1);
133#elif defined(CONFIG_MACH_SUN5I)
134 sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
135 sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
136 clock_twi_onoff(2, 1);
137#elif defined(CONFIG_MACH_SUN6I)
138 sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
139 sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
140 clock_twi_onoff(2, 1);
141#elif defined(CONFIG_MACH_SUN8I)
142 sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
143 sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
144 clock_twi_onoff(2, 1);
145#endif
146#endif
147
148#ifdef CONFIG_I2C3_ENABLE
149#if defined(CONFIG_MACH_SUN6I)
150 sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
151 sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
152 clock_twi_onoff(3, 1);
153#elif defined(CONFIG_MACH_SUN7I) || \
154 defined(CONFIG_MACH_SUN8I_R40)
155 sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
156 sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
157 clock_twi_onoff(3, 1);
158#endif
159#endif
160
161#ifdef CONFIG_I2C4_ENABLE
162#if defined(CONFIG_MACH_SUN7I) || \
163 defined(CONFIG_MACH_SUN8I_R40)
164 sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
165 sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
166 clock_twi_onoff(4, 1);
167#endif
168#endif
169
170#ifdef CONFIG_R_I2C_ENABLE
171 clock_twi_onoff(5, 1);
172 sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
173 sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
174#endif
175}
176
Maxime Ripard9ba2ac72018-01-23 21:17:03 +0100177#if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
178enum env_location env_get_location(enum env_operation op, int prio)
179{
180 switch (prio) {
181 case 0:
182 return ENVL_FAT;
183
184 case 1:
185 return ENVL_MMC;
186
187 default:
188 return ENVL_UNKNOWN;
189 }
190}
191#endif
192
Ian Campbell6efe3692014-05-05 11:52:26 +0100193/* add board specific code here */
194int board_init(void)
195{
Mylène Josserand147c6062017-04-02 12:59:10 +0200196 __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
Ian Campbell6efe3692014-05-05 11:52:26 +0100197
198 gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
199
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200200#ifndef CONFIG_ARM64
Ian Campbell6efe3692014-05-05 11:52:26 +0100201 asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
202 debug("id_pfr1: 0x%08x\n", id_pfr1);
203 /* Generic Timer Extension available? */
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200204 if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
205 uint32_t freq;
206
Ian Campbell6efe3692014-05-05 11:52:26 +0100207 debug("Setting CNTFRQ\n");
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200208
209 /*
210 * CNTFRQ is a secure register, so we will crash if we try to
211 * write this from the non-secure world (read is OK, though).
212 * In case some bootcode has already set the correct value,
213 * we avoid the risk of writing to it.
214 */
215 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
Andre Przywara70c78932017-02-16 01:20:19 +0000216 if (freq != COUNTER_FREQUENCY) {
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200217 debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
Andre Przywara70c78932017-02-16 01:20:19 +0000218 freq, COUNTER_FREQUENCY);
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200219#ifdef CONFIG_NON_SECURE
220 printf("arch timer frequency is wrong, but cannot adjust it\n");
221#else
222 asm volatile("mcr p15, 0, %0, c14, c0, 0"
Andre Przywara70c78932017-02-16 01:20:19 +0000223 : : "r"(COUNTER_FREQUENCY));
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200224#endif
225 }
Ian Campbell6efe3692014-05-05 11:52:26 +0100226 }
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200227#endif /* !CONFIG_ARM64 */
Ian Campbell6efe3692014-05-05 11:52:26 +0100228
Hans de Goede3ae1d132015-04-25 17:25:14 +0200229 ret = axp_gpio_init();
230 if (ret)
231 return ret;
232
Hans de Goede9c34c3e2016-03-22 20:10:30 +0100233#ifdef CONFIG_SATAPWR
Mylène Josserand628426a2017-04-02 12:59:09 +0200234 satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
235 gpio_request(satapwr_pin, "satapwr");
236 gpio_direction_output(satapwr_pin, 1);
Werner Böllmanne58f8302017-11-10 19:14:20 +0530237 /* Give attached sata device time to power-up to avoid link timeouts */
238 mdelay(500);
Hans de Goede9c34c3e2016-03-22 20:10:30 +0100239#endif
Hans de Goede42cbbe32016-03-17 13:53:03 +0100240#ifdef CONFIG_MACPWR
Mylène Josserand147c6062017-04-02 12:59:10 +0200241 macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
242 gpio_request(macpwr_pin, "macpwr");
243 gpio_direction_output(macpwr_pin, 1);
Hans de Goede42cbbe32016-03-17 13:53:03 +0100244#endif
245
Jernej Skrabec9220d502017-04-27 00:03:36 +0200246#ifdef CONFIG_DM_I2C
247 /*
248 * Temporary workaround for enabling I2C clocks until proper sunxi DM
249 * clk, reset and pinctrl drivers land.
250 */
251 i2c_init_board();
252#endif
253
Hans de Goeded9d05652015-04-23 23:23:50 +0200254 /* Uses dm gpio code so do this here and not in i2c_init_board() */
255 return soft_i2c_board_init();
Ian Campbell6efe3692014-05-05 11:52:26 +0100256}
257
258int dram_init(void)
259{
260 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE);
261
262 return 0;
263}
264
Boris Brezillon57f20382016-06-15 21:09:23 +0200265#if defined(CONFIG_NAND_SUNXI)
Karol Gugala7bea8932015-07-23 14:33:01 +0200266static void nand_pinmux_setup(void)
267{
268 unsigned int pin;
Karol Gugala7bea8932015-07-23 14:33:01 +0200269
Hans de Goeded2236782015-08-15 13:17:49 +0200270 for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
Karol Gugala7bea8932015-07-23 14:33:01 +0200271 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
272
Hans de Goeded2236782015-08-15 13:17:49 +0200273#if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
274 for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
275 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
276#endif
277 /* sun4i / sun7i do have a PC23, but it is not used for nand,
278 * only sun7i has a PC24 */
279#ifdef CONFIG_MACH_SUN7I
Karol Gugala7bea8932015-07-23 14:33:01 +0200280 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
Hans de Goeded2236782015-08-15 13:17:49 +0200281#endif
Karol Gugala7bea8932015-07-23 14:33:01 +0200282}
283
284static void nand_clock_setup(void)
285{
286 struct sunxi_ccm_reg *const ccm =
287 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
Hans de Goedee5561a82015-08-15 11:58:03 +0200288
Karol Gugala7bea8932015-07-23 14:33:01 +0200289 setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
Miquel Raynalebeeb802018-02-28 20:51:53 +0100290#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
291 defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
292 setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
293#endif
Karol Gugala7bea8932015-07-23 14:33:01 +0200294 setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
295}
Hans de Goede5ed52f62015-08-15 11:55:26 +0200296
297void board_nand_init(void)
298{
299 nand_pinmux_setup();
300 nand_clock_setup();
Boris Brezillon57f20382016-06-15 21:09:23 +0200301#ifndef CONFIG_SPL_BUILD
302 sunxi_nand_init();
303#endif
Hans de Goede5ed52f62015-08-15 11:55:26 +0200304}
Karol Gugala7bea8932015-07-23 14:33:01 +0200305#endif
306
Masahiro Yamada0a780172017-05-09 20:31:39 +0900307#ifdef CONFIG_MMC
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100308static void mmc_pinmux_setup(int sdc)
309{
310 unsigned int pin;
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100311 __maybe_unused int pins;
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100312
313 switch (sdc) {
314 case 0:
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100315 /* SDC0: PF0-PF5 */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100316 for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100317 sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100318 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
319 sunxi_gpio_set_drv(pin, 2);
320 }
321 break;
322
323 case 1:
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100324 pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
325
Chen-Yu Tsai111bc592016-11-30 16:28:34 +0800326#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
327 defined(CONFIG_MACH_SUN8I_R40)
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100328 if (pins == SUNXI_GPIO_H) {
329 /* SDC1: PH22-PH-27 */
330 for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
331 sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
332 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
333 sunxi_gpio_set_drv(pin, 2);
334 }
335 } else {
336 /* SDC1: PG0-PG5 */
337 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
338 sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
339 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
340 sunxi_gpio_set_drv(pin, 2);
341 }
342 }
343#elif defined(CONFIG_MACH_SUN5I)
344 /* SDC1: PG3-PG8 */
Hans de Goede4dccfd42014-10-03 16:44:57 +0200345 for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100346 sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100347 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
348 sunxi_gpio_set_drv(pin, 2);
349 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100350#elif defined(CONFIG_MACH_SUN6I)
351 /* SDC1: PG0-PG5 */
352 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
353 sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
354 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
355 sunxi_gpio_set_drv(pin, 2);
356 }
357#elif defined(CONFIG_MACH_SUN8I)
358 if (pins == SUNXI_GPIO_D) {
359 /* SDC1: PD2-PD7 */
360 for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
361 sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
362 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
363 sunxi_gpio_set_drv(pin, 2);
364 }
365 } else {
366 /* SDC1: PG0-PG5 */
367 for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
368 sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
369 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
370 sunxi_gpio_set_drv(pin, 2);
371 }
372 }
373#endif
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100374 break;
375
376 case 2:
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100377 pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
378
379#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
380 /* SDC2: PC6-PC11 */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100381 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
Paul Kocialkowskiae358a42015-03-22 18:12:22 +0100382 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100383 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
384 sunxi_gpio_set_drv(pin, 2);
385 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100386#elif defined(CONFIG_MACH_SUN5I)
387 if (pins == SUNXI_GPIO_E) {
388 /* SDC2: PE4-PE9 */
389 for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
390 sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
391 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
392 sunxi_gpio_set_drv(pin, 2);
393 }
394 } else {
395 /* SDC2: PC6-PC15 */
396 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
397 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
398 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
399 sunxi_gpio_set_drv(pin, 2);
400 }
401 }
402#elif defined(CONFIG_MACH_SUN6I)
403 if (pins == SUNXI_GPIO_A) {
404 /* SDC2: PA9-PA14 */
405 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
406 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
407 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
408 sunxi_gpio_set_drv(pin, 2);
409 }
410 } else {
411 /* SDC2: PC6-PC15, PC24 */
412 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
413 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
414 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
415 sunxi_gpio_set_drv(pin, 2);
416 }
417
418 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
419 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
420 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
421 }
Chen-Yu Tsai111bc592016-11-30 16:28:34 +0800422#elif defined(CONFIG_MACH_SUN8I_R40)
423 /* SDC2: PC6-PC15, PC24 */
424 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
425 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
426 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
427 sunxi_gpio_set_drv(pin, 2);
428 }
429
430 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
431 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
432 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200433#elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100434 /* SDC2: PC5-PC6, PC8-PC16 */
435 for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
436 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
437 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
438 sunxi_gpio_set_drv(pin, 2);
439 }
440
441 for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
442 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
443 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
444 sunxi_gpio_set_drv(pin, 2);
445 }
Philipp Tomsicha0c7c712016-10-28 18:21:33 +0800446#elif defined(CONFIG_MACH_SUN9I)
447 /* SDC2: PC6-PC16 */
448 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
449 sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
450 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
451 sunxi_gpio_set_drv(pin, 2);
452 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100453#endif
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100454 break;
455
456 case 3:
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100457 pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
458
Chen-Yu Tsai111bc592016-11-30 16:28:34 +0800459#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
460 defined(CONFIG_MACH_SUN8I_R40)
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100461 /* SDC3: PI4-PI9 */
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100462 for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100463 sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100464 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
465 sunxi_gpio_set_drv(pin, 2);
466 }
Paul Kocialkowskid390d8c2015-03-22 18:12:23 +0100467#elif defined(CONFIG_MACH_SUN6I)
468 if (pins == SUNXI_GPIO_A) {
469 /* SDC3: PA9-PA14 */
470 for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
471 sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
472 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
473 sunxi_gpio_set_drv(pin, 2);
474 }
475 } else {
476 /* SDC3: PC6-PC15, PC24 */
477 for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
478 sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
479 sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
480 sunxi_gpio_set_drv(pin, 2);
481 }
482
483 sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
484 sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
485 sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
486 }
487#endif
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100488 break;
489
490 default:
491 printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
492 break;
493 }
494}
495
496int board_mmc_init(bd_t *bis)
497{
Hans de Goede63deaa82014-10-02 21:13:54 +0200498 __maybe_unused struct mmc *mmc0, *mmc1;
499 __maybe_unused char buf[512];
500
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100501 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
Hans de Goede63deaa82014-10-02 21:13:54 +0200502 mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
503 if (!mmc0)
504 return -1;
505
Hans de Goedeaf593e42014-10-02 20:43:50 +0200506#if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100507 mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
Hans de Goede63deaa82014-10-02 21:13:54 +0200508 mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
509 if (!mmc1)
510 return -1;
511#endif
512
Ian Campbellb4e9f2f2014-05-05 14:42:31 +0100513 return 0;
514}
515#endif
516
Ian Campbell6efe3692014-05-05 11:52:26 +0100517#ifdef CONFIG_SPL_BUILD
518void sunxi_board_init(void)
519{
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200520 int power_failed = 0;
Ian Campbell6efe3692014-05-05 11:52:26 +0100521
Jelle van der Waa3f3a3092016-02-23 18:47:19 +0100522#ifdef CONFIG_SY8106A_POWER
523 power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
524#endif
525
vishnupatekar1895dfd2015-11-29 01:07:22 +0800526#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800527 defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
528 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200529 power_failed = axp_init();
530
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800531#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
532 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200533 power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
Hans de Goede1f247362014-06-13 22:55:51 +0200534#endif
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200535 power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
536 power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
vishnupatekar1895dfd2015-11-29 01:07:22 +0800537#if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200538 power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200539#endif
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800540#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
541 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200542 power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
Oliver Schinagld3a558d2013-07-26 12:56:58 +0200543#endif
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200544
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800545#if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
546 defined CONFIG_AXP818_POWER
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200547 power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
548#endif
549 power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
Chen-Yu Tsaic05aa392016-01-12 14:42:40 +0800550#if !defined(CONFIG_AXP152_POWER)
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200551 power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
552#endif
553#ifdef CONFIG_AXP209_POWER
554 power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
555#endif
556
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800557#if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
558 defined(CONFIG_AXP818_POWER)
Chen-Yu Tsai2e6911f2016-01-12 14:42:37 +0800559 power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
560 power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800561#if !defined CONFIG_AXP809_POWER
Chen-Yu Tsai2e6911f2016-01-12 14:42:37 +0800562 power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
563 power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800564#endif
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200565 power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
566 power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
567 power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
568#endif
Chen-Yu Tsaid028fba2016-03-30 00:26:48 +0800569
570#ifdef CONFIG_AXP818_POWER
571 power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
572 power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
573 power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
Chen-Yu Tsaif1e66e72016-05-02 10:28:15 +0800574#endif
575
576#if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
Chen-Yu Tsai0e3efd32016-05-02 10:28:12 +0800577 power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
Chen-Yu Tsaid028fba2016-03-30 00:26:48 +0800578#endif
Hans de Goeded9ee84b2015-10-03 15:18:33 +0200579#endif
Ian Campbell6efe3692014-05-05 11:52:26 +0100580 printf("DRAM:");
Andre Przywara52f48662017-04-26 01:32:43 +0100581 gd->ram_size = sunxi_dram_init();
582 printf(" %d MiB\n", (int)(gd->ram_size >> 20));
583 if (!gd->ram_size)
Ian Campbell6efe3692014-05-05 11:52:26 +0100584 hang();
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200585
586 /*
587 * Only clock up the CPU to full speed if we are reasonably
588 * assured it's being powered with suitable core voltage
589 */
590 if (!power_failed)
Iain Paton630df142015-03-28 10:26:38 +0000591 clock_set_pll1(CONFIG_SYS_CLK_FREQ);
Henrik Nordstromaa382ad2014-06-13 22:55:50 +0200592 else
593 printf("Failed to set core voltage! Can't set CPU frequency\n");
Ian Campbell6efe3692014-05-05 11:52:26 +0100594}
595#endif
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200596
Paul Kocialkowskidbbccaf2015-03-22 18:07:13 +0100597#ifdef CONFIG_USB_GADGET
598int g_dnl_board_usb_cable_connected(void)
599{
Jagan Teki73a3ecf2018-05-07 13:03:36 +0530600 struct udevice *dev;
601 struct phy phy;
602 int ret;
603
604 ret = uclass_get_device(UCLASS_USB_DEV_GENERIC, 0, &dev);
605 if (ret) {
606 pr_err("%s: Cannot find USB device\n", __func__);
607 return ret;
608 }
609
610 ret = generic_phy_get_by_name(dev, "usb", &phy);
611 if (ret) {
612 pr_err("failed to get %s USB PHY\n", dev->name);
613 return ret;
614 }
615
616 ret = generic_phy_init(&phy);
617 if (ret) {
618 pr_err("failed to init %s USB PHY\n", dev->name);
619 return ret;
620 }
621
622 ret = sun4i_usb_phy_vbus_detect(&phy);
623 if (ret == 1) {
624 pr_err("A charger is plugged into the OTG\n");
625 return -ENODEV;
626 }
627
628 return ret;
Paul Kocialkowskidbbccaf2015-03-22 18:07:13 +0100629}
630#endif
631
Paul Kocialkowski99ae0f62015-03-28 18:35:36 +0100632#ifdef CONFIG_SERIAL_TAG
633void get_board_serial(struct tag_serialnr *serialnr)
634{
635 char *serial_string;
636 unsigned long long serial;
637
Simon Glass64b723f2017-08-03 12:22:12 -0600638 serial_string = env_get("serial#");
Paul Kocialkowski99ae0f62015-03-28 18:35:36 +0100639
640 if (serial_string) {
641 serial = simple_strtoull(serial_string, NULL, 16);
642
643 serialnr->high = (unsigned int) (serial >> 32);
644 serialnr->low = (unsigned int) (serial & 0xffffffff);
645 } else {
646 serialnr->high = 0;
647 serialnr->low = 0;
648 }
649}
650#endif
651
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200652/*
653 * Check the SPL header for the "sunxi" variant. If found: parse values
654 * that might have been passed by the loader ("fel" utility), and update
655 * the environment accordingly.
656 */
657static void parse_spl_header(const uint32_t spl_addr)
658{
Siarhei Siamashka26c50fb2016-03-29 17:29:10 +0200659 struct boot_file_head *spl = (void *)(ulong)spl_addr;
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200660 if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
661 return; /* signature mismatch, no usable header */
662
663 uint8_t spl_header_version = spl->spl_signature[3];
664 if (spl_header_version != SPL_HEADER_VERSION) {
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200665 printf("sunxi SPL version mismatch: expected %u, got %u\n",
666 SPL_HEADER_VERSION, spl_header_version);
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200667 return;
668 }
669 if (!spl->fel_script_address)
670 return;
671
672 if (spl->fel_uEnv_length != 0) {
673 /*
674 * data is expected in uEnv.txt compatible format, so "env
675 * import -t" the string(s) at fel_script_address right away.
676 */
Andre Przywaraac4e6732016-09-05 01:32:41 +0100677 himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200678 spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
679 return;
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200680 }
Bernhard Nortmanne9bbbe82016-06-09 07:37:35 +0200681 /* otherwise assume .scr format (mkimage-type script) */
Simon Glass4d949a22017-08-03 12:22:10 -0600682 env_set_hex("fel_scriptaddr", spl->fel_script_address);
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200683}
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200684
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200685/*
686 * Note this function gets called multiple times.
687 * It must not make any changes to env variables which already exist.
688 */
689static void setup_environment(const void *fdt)
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200690{
Paul Kocialkowski92935942015-03-28 18:35:35 +0100691 char serial_string[17] = { 0 };
Hans de Goede11d70982014-11-26 00:04:24 +0100692 unsigned int sid[4];
Paul Kocialkowski92935942015-03-28 18:35:35 +0100693 uint8_t mac_addr[6];
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200694 char ethaddr[16];
695 int i, ret;
Bernhard Nortmannead498a2015-09-17 18:52:52 +0200696
Paul Kocialkowski92935942015-03-28 18:35:35 +0100697 ret = sunxi_get_sid(sid);
Hans de Goedee5fe5482016-07-29 11:47:03 +0200698 if (ret == 0 && sid[0] != 0) {
699 /*
700 * The single words 1 - 3 of the SID have quite a few bits
701 * which are the same on many models, so we take a crc32
702 * of all 3 words, to get a more unique value.
703 *
704 * Note we only do this on newer SoCs as we cannot change
705 * the algorithm on older SoCs since those have been using
706 * fixed mac-addresses based on only using word 3 for a
707 * long time and changing a fixed mac-address with an
708 * u-boot update is not good.
709 */
710#if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
711 !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
712 !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
713 sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
714#endif
715
Hans de Goedeabca8432016-07-27 17:58:06 +0200716 /* Ensure the NIC specific bytes of the mac are not all 0 */
717 if ((sid[3] & 0xffffff) == 0)
718 sid[3] |= 0x800000;
719
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200720 for (i = 0; i < 4; i++) {
721 sprintf(ethaddr, "ethernet%d", i);
722 if (!fdt_get_alias(fdt, ethaddr))
723 continue;
724
725 if (i == 0)
726 strcpy(ethaddr, "ethaddr");
727 else
728 sprintf(ethaddr, "eth%daddr", i);
729
Simon Glass64b723f2017-08-03 12:22:12 -0600730 if (env_get(ethaddr))
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200731 continue;
732
Paul Kocialkowski92935942015-03-28 18:35:35 +0100733 /* Non OUI / registered MAC address */
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200734 mac_addr[0] = (i << 4) | 0x02;
Paul Kocialkowski92935942015-03-28 18:35:35 +0100735 mac_addr[1] = (sid[0] >> 0) & 0xff;
736 mac_addr[2] = (sid[3] >> 24) & 0xff;
737 mac_addr[3] = (sid[3] >> 16) & 0xff;
738 mac_addr[4] = (sid[3] >> 8) & 0xff;
739 mac_addr[5] = (sid[3] >> 0) & 0xff;
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200740
Simon Glass8551d552017-08-03 12:22:11 -0600741 eth_env_set_enetaddr(ethaddr, mac_addr);
Paul Kocialkowski92935942015-03-28 18:35:35 +0100742 }
743
Simon Glass64b723f2017-08-03 12:22:12 -0600744 if (!env_get("serial#")) {
Paul Kocialkowski92935942015-03-28 18:35:35 +0100745 snprintf(serial_string, sizeof(serial_string),
746 "%08x%08x", sid[0], sid[3]);
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200747
Simon Glass6a38e412017-08-03 12:22:09 -0600748 env_set("serial#", serial_string);
Paul Kocialkowski92935942015-03-28 18:35:35 +0100749 }
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200750 }
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200751}
752
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200753int misc_init_r(void)
754{
755 __maybe_unused int ret;
Maxime Ripardae56d972017-08-23 10:08:29 +0200756 uint boot;
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200757
Simon Glass6a38e412017-08-03 12:22:09 -0600758 env_set("fel_booted", NULL);
759 env_set("fel_scriptaddr", NULL);
Maxime Ripard65cefba2017-08-23 10:12:22 +0200760 env_set("mmc_bootdev", NULL);
Maxime Ripardae56d972017-08-23 10:08:29 +0200761
762 boot = sunxi_get_boot_device();
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200763 /* determine if we are running in FEL mode */
Maxime Ripardae56d972017-08-23 10:08:29 +0200764 if (boot == BOOT_DEVICE_BOARD) {
Simon Glass6a38e412017-08-03 12:22:09 -0600765 env_set("fel_booted", "1");
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200766 parse_spl_header(SPL_ADDR);
Maxime Ripard65cefba2017-08-23 10:12:22 +0200767 /* or if we booted from MMC, and which one */
768 } else if (boot == BOOT_DEVICE_MMC1) {
769 env_set("mmc_bootdev", "0");
770 } else if (boot == BOOT_DEVICE_MMC2) {
771 env_set("mmc_bootdev", "1");
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200772 }
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200773
774 setup_environment(gd->fdt_blob);
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200775
Icenowy Zhengf4116b62017-09-28 22:16:38 +0800776#ifdef CONFIG_USB_ETHER
Maxime Ripardf54aba32017-09-06 22:25:03 +0200777 usb_ether_init();
Icenowy Zhengf4116b62017-09-28 22:16:38 +0800778#endif
Maxime Ripardf54aba32017-09-06 22:25:03 +0200779
Jonathan Liuabc1aae2014-06-14 08:59:09 +0200780 return 0;
781}
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200782
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200783int ft_board_setup(void *blob, bd_t *bd)
784{
Hans de Goede48a234a2016-03-22 22:51:52 +0100785 int __maybe_unused r;
786
Hans de Goededa0ff7c2016-06-26 13:34:42 +0200787 /*
788 * Call setup_environment again in case the boot fdt has
789 * ethernet aliases the u-boot copy does not have.
790 */
791 setup_environment(blob);
792
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200793#ifdef CONFIG_VIDEO_DT_SIMPLEFB
Hans de Goede48a234a2016-03-22 22:51:52 +0100794 r = sunxi_simplefb_setup(blob);
795 if (r)
796 return r;
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200797#endif
Hans de Goede48a234a2016-03-22 22:51:52 +0100798 return 0;
Luc Verhaegen4869a8c2014-08-13 07:55:07 +0200799}
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100800
801#ifdef CONFIG_SPL_LOAD_FIT
802int board_fit_config_name_match(const char *name)
803{
Andre Przywara4f99ea62017-04-26 01:32:50 +0100804 struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
805 const char *cmp_str = (void *)(ulong)SPL_ADDR;
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100806
Andre Przywara4f99ea62017-04-26 01:32:50 +0100807 /* Check if there is a DT name stored in the SPL header and use that. */
808 if (spl->dt_name_offset) {
809 cmp_str += spl->dt_name_offset;
810 } else {
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100811#ifdef CONFIG_DEFAULT_DEVICE_TREE
Andre Przywara4f99ea62017-04-26 01:32:50 +0100812 cmp_str = CONFIG_DEFAULT_DEVICE_TREE;
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100813#else
Andre Przywara4f99ea62017-04-26 01:32:50 +0100814 return 0;
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100815#endif
Andre Przywara4f99ea62017-04-26 01:32:50 +0100816 };
Andre Przywara1bd5ca32017-04-26 01:32:44 +0100817
818/* Differentiate the two Pine64 board DTs by their DRAM size. */
819 if (strstr(name, "-pine64") && strstr(cmp_str, "-pine64")) {
820 if ((gd->ram_size > 512 * 1024 * 1024))
821 return !strstr(name, "plus");
822 else
823 return !!strstr(name, "plus");
824 } else {
825 return strcmp(name, cmp_str);
826 }
827}
828#endif