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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
TsiChungLiewb859ef12007-08-16 19:23:50 -05002/*
3 *
Alison Wangd132fe62012-03-26 21:49:06 +00004 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiewb859ef12007-08-16 19:23:50 -05005 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
TsiChungLiewb859ef12007-08-16 19:23:50 -05006 */
7
8/* CPU specific interrupt routine */
9#include <common.h>
10#include <asm/immap.h>
Alison Wangd132fe62012-03-26 21:49:06 +000011#include <asm/io.h>
TsiChungLiewb859ef12007-08-16 19:23:50 -050012
13int interrupt_init(void)
14{
Alison Wangd132fe62012-03-26 21:49:06 +000015 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
TsiChungLiewb859ef12007-08-16 19:23:50 -050016
17 /* Make sure all interrupts are disabled */
Alison Wangd132fe62012-03-26 21:49:06 +000018 setbits_be32(&intp->imrl0, 0x1);
TsiChungLiewb859ef12007-08-16 19:23:50 -050019
20 enable_interrupts();
21 return 0;
22}
23
24#if defined(CONFIG_MCFTMR)
25void dtimer_intr_setup(void)
26{
Alison Wangd132fe62012-03-26 21:49:06 +000027 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
TsiChungLiewb859ef12007-08-16 19:23:50 -050028
Alison Wangd132fe62012-03-26 21:49:06 +000029 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
30 clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
31 clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
TsiChungLiewb859ef12007-08-16 19:23:50 -050032}
33#endif