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git01.mediatek.com / filogic / uboot / 1523ac45a120c5be2f45fb2df16c9785ff1fa848 / . / drivers / pinctrl / starfive / pinctrl-jh7110-sys.c
blob: dafba65eae11b969aa5bd709bcf1e3158f754ffb [file] [log] [blame]
Kuan Lim Leeec2b8f22023-03-29 11:42:15 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Pinctrl / GPIO driver for StarFive JH7110 SoC
4 *
5 * Copyright (C) 2022 StarFive Technology Co., Ltd.
6 * Author: Lee Kuan Lim <kuanlim.lee@starfivetech.com>
7 * Author: Jianlong Huang <jianlong.huang@starfivetech.com>
8 */
9
10#include <dm/read.h>
11#include <dm/device_compat.h>
12#include <linux/io.h>
13
14#include <dt-bindings/pinctrl/pinctrl-starfive-jh7110.h>
15#include "pinctrl-starfive.h"
16
17#define JH7110_SYS_NGPIO 64
18#define JH7110_SYS_GC_BASE 0
19
20/* registers */
21#define JH7110_SYS_DOEN 0x000
22#define JH7110_SYS_DOUT 0x040
23#define JH7110_SYS_GPI 0x080
24#define JH7110_SYS_GPIOIN 0x118
25
26#define JH7110_SYS_GPIOEN 0x0dc
27#define JH7110_SYS_GPIOIS0 0x0e0
28#define JH7110_SYS_GPIOIS1 0x0e4
29#define JH7110_SYS_GPIOIC0 0x0e8
30#define JH7110_SYS_GPIOIC1 0x0ec
31#define JH7110_SYS_GPIOIBE0 0x0f0
32#define JH7110_SYS_GPIOIBE1 0x0f4
33#define JH7110_SYS_GPIOIEV0 0x0f8
34#define JH7110_SYS_GPIOIEV1 0x0fc
35#define JH7110_SYS_GPIOIE0 0x100
36#define JH7110_SYS_GPIOIE1 0x104
37#define JH7110_SYS_GPIORIS0 0x108
38#define JH7110_SYS_GPIORIS1 0x10c
39#define JH7110_SYS_GPIOMIS0 0x110
40#define JH7110_SYS_GPIOMIS1 0x114
41
42#define SYS_GPO_PDA_0_74_CFG 0x120
43#define SYS_GPO_PDA_89_94_CFG 0x284
44
45static const struct starfive_pinctrl_pin jh7110_sys_pins[] = {
46 STARFIVE_PINCTRL(PAD_GPIO0, "GPIO0"),
47 STARFIVE_PINCTRL(PAD_GPIO1, "GPIO1"),
48 STARFIVE_PINCTRL(PAD_GPIO2, "GPIO2"),
49 STARFIVE_PINCTRL(PAD_GPIO3, "GPIO3"),
50 STARFIVE_PINCTRL(PAD_GPIO4, "GPIO4"),
51 STARFIVE_PINCTRL(PAD_GPIO5, "GPIO5"),
52 STARFIVE_PINCTRL(PAD_GPIO6, "GPIO6"),
53 STARFIVE_PINCTRL(PAD_GPIO7, "GPIO7"),
54 STARFIVE_PINCTRL(PAD_GPIO8, "GPIO8"),
55 STARFIVE_PINCTRL(PAD_GPIO9, "GPIO9"),
56 STARFIVE_PINCTRL(PAD_GPIO10, "GPIO10"),
57 STARFIVE_PINCTRL(PAD_GPIO11, "GPIO11"),
58 STARFIVE_PINCTRL(PAD_GPIO12, "GPIO12"),
59 STARFIVE_PINCTRL(PAD_GPIO13, "GPIO13"),
60 STARFIVE_PINCTRL(PAD_GPIO14, "GPIO14"),
61 STARFIVE_PINCTRL(PAD_GPIO15, "GPIO15"),
62 STARFIVE_PINCTRL(PAD_GPIO16, "GPIO16"),
63 STARFIVE_PINCTRL(PAD_GPIO17, "GPIO17"),
64 STARFIVE_PINCTRL(PAD_GPIO18, "GPIO18"),
65 STARFIVE_PINCTRL(PAD_GPIO19, "GPIO19"),
66 STARFIVE_PINCTRL(PAD_GPIO20, "GPIO20"),
67 STARFIVE_PINCTRL(PAD_GPIO21, "GPIO21"),
68 STARFIVE_PINCTRL(PAD_GPIO22, "GPIO22"),
69 STARFIVE_PINCTRL(PAD_GPIO23, "GPIO23"),
70 STARFIVE_PINCTRL(PAD_GPIO24, "GPIO24"),
71 STARFIVE_PINCTRL(PAD_GPIO25, "GPIO25"),
72 STARFIVE_PINCTRL(PAD_GPIO26, "GPIO26"),
73 STARFIVE_PINCTRL(PAD_GPIO27, "GPIO27"),
74 STARFIVE_PINCTRL(PAD_GPIO28, "GPIO28"),
75 STARFIVE_PINCTRL(PAD_GPIO29, "GPIO29"),
76 STARFIVE_PINCTRL(PAD_GPIO30, "GPIO30"),
77 STARFIVE_PINCTRL(PAD_GPIO31, "GPIO31"),
78 STARFIVE_PINCTRL(PAD_GPIO32, "GPIO32"),
79 STARFIVE_PINCTRL(PAD_GPIO33, "GPIO33"),
80 STARFIVE_PINCTRL(PAD_GPIO34, "GPIO34"),
81 STARFIVE_PINCTRL(PAD_GPIO35, "GPIO35"),
82 STARFIVE_PINCTRL(PAD_GPIO36, "GPIO36"),
83 STARFIVE_PINCTRL(PAD_GPIO37, "GPIO37"),
84 STARFIVE_PINCTRL(PAD_GPIO38, "GPIO38"),
85 STARFIVE_PINCTRL(PAD_GPIO39, "GPIO39"),
86 STARFIVE_PINCTRL(PAD_GPIO40, "GPIO40"),
87 STARFIVE_PINCTRL(PAD_GPIO41, "GPIO41"),
88 STARFIVE_PINCTRL(PAD_GPIO42, "GPIO42"),
89 STARFIVE_PINCTRL(PAD_GPIO43, "GPIO43"),
90 STARFIVE_PINCTRL(PAD_GPIO44, "GPIO44"),
91 STARFIVE_PINCTRL(PAD_GPIO45, "GPIO45"),
92 STARFIVE_PINCTRL(PAD_GPIO46, "GPIO46"),
93 STARFIVE_PINCTRL(PAD_GPIO47, "GPIO47"),
94 STARFIVE_PINCTRL(PAD_GPIO48, "GPIO48"),
95 STARFIVE_PINCTRL(PAD_GPIO49, "GPIO49"),
96 STARFIVE_PINCTRL(PAD_GPIO50, "GPIO50"),
97 STARFIVE_PINCTRL(PAD_GPIO51, "GPIO51"),
98 STARFIVE_PINCTRL(PAD_GPIO52, "GPIO52"),
99 STARFIVE_PINCTRL(PAD_GPIO53, "GPIO53"),
100 STARFIVE_PINCTRL(PAD_GPIO54, "GPIO54"),
101 STARFIVE_PINCTRL(PAD_GPIO55, "GPIO55"),
102 STARFIVE_PINCTRL(PAD_GPIO56, "GPIO56"),
103 STARFIVE_PINCTRL(PAD_GPIO57, "GPIO57"),
104 STARFIVE_PINCTRL(PAD_GPIO58, "GPIO58"),
105 STARFIVE_PINCTRL(PAD_GPIO59, "GPIO59"),
106 STARFIVE_PINCTRL(PAD_GPIO60, "GPIO60"),
107 STARFIVE_PINCTRL(PAD_GPIO61, "GPIO61"),
108 STARFIVE_PINCTRL(PAD_GPIO62, "GPIO62"),
109 STARFIVE_PINCTRL(PAD_GPIO63, "GPIO63"),
110 STARFIVE_PINCTRL(PAD_SD0_CLK, "SD0_CLK"),
111 STARFIVE_PINCTRL(PAD_SD0_CMD, "SD0_CMD"),
112 STARFIVE_PINCTRL(PAD_SD0_DATA0, "SD0_DATA0"),
113 STARFIVE_PINCTRL(PAD_SD0_DATA1, "SD0_DATA1"),
114 STARFIVE_PINCTRL(PAD_SD0_DATA2, "SD0_DATA2"),
115 STARFIVE_PINCTRL(PAD_SD0_DATA3, "SD0_DATA3"),
116 STARFIVE_PINCTRL(PAD_SD0_DATA4, "SD0_DATA4"),
117 STARFIVE_PINCTRL(PAD_SD0_DATA5, "SD0_DATA5"),
118 STARFIVE_PINCTRL(PAD_SD0_DATA6, "SD0_DATA6"),
119 STARFIVE_PINCTRL(PAD_SD0_DATA7, "SD0_DATA7"),
120 STARFIVE_PINCTRL(PAD_SD0_STRB, "SD0_STRB"),
121 STARFIVE_PINCTRL(PAD_GMAC1_MDC, "GMAC1_MDC"),
122 STARFIVE_PINCTRL(PAD_GMAC1_MDIO, "GMAC1_MDIO"),
123 STARFIVE_PINCTRL(PAD_GMAC1_RXD0, "GMAC1_RXD0"),
124 STARFIVE_PINCTRL(PAD_GMAC1_RXD1, "GMAC1_RXD1"),
125 STARFIVE_PINCTRL(PAD_GMAC1_RXD2, "GMAC1_RXD2"),
126 STARFIVE_PINCTRL(PAD_GMAC1_RXD3, "GMAC1_RXD3"),
127 STARFIVE_PINCTRL(PAD_GMAC1_RXDV, "GMAC1_RXDV"),
128 STARFIVE_PINCTRL(PAD_GMAC1_RXC, "GMAC1_RXC"),
129 STARFIVE_PINCTRL(PAD_GMAC1_TXD0, "GMAC1_TXD0"),
130 STARFIVE_PINCTRL(PAD_GMAC1_TXD1, "GMAC1_TXD1"),
131 STARFIVE_PINCTRL(PAD_GMAC1_TXD2, "GMAC1_TXD2"),
132 STARFIVE_PINCTRL(PAD_GMAC1_TXD3, "GMAC1_TXD3"),
133 STARFIVE_PINCTRL(PAD_GMAC1_TXEN, "GMAC1_TXEN"),
134 STARFIVE_PINCTRL(PAD_GMAC1_TXC, "GMAC1_TXC"),
135 STARFIVE_PINCTRL(PAD_QSPI_SCLK, "QSPI_SCLK"),
136 STARFIVE_PINCTRL(PAD_QSPI_CS0, "QSPI_CS0"),
137 STARFIVE_PINCTRL(PAD_QSPI_DATA0, "QSPI_DATA0"),
138 STARFIVE_PINCTRL(PAD_QSPI_DATA1, "QSPI_DATA1"),
139 STARFIVE_PINCTRL(PAD_QSPI_DATA2, "QSPI_DATA2"),
140 STARFIVE_PINCTRL(PAD_QSPI_DATA3, "QSPI_DATA3"),
141};
142
143struct jh7110_func_sel {
144 u16 offset;
145 u8 shift;
146 u8 max;
147};
148
149static const struct jh7110_func_sel
150 jh7110_sys_func_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
151 [PAD_GMAC1_RXC] = { 0x29c, 0, 1 },
152 [PAD_GPIO10] = { 0x29c, 2, 3 },
153 [PAD_GPIO11] = { 0x29c, 5, 3 },
154 [PAD_GPIO12] = { 0x29c, 8, 3 },
155 [PAD_GPIO13] = { 0x29c, 11, 3 },
156 [PAD_GPIO14] = { 0x29c, 14, 3 },
157 [PAD_GPIO15] = { 0x29c, 17, 3 },
158 [PAD_GPIO16] = { 0x29c, 20, 3 },
159 [PAD_GPIO17] = { 0x29c, 23, 3 },
160 [PAD_GPIO18] = { 0x29c, 26, 3 },
161 [PAD_GPIO19] = { 0x29c, 29, 3 },
162
163 [PAD_GPIO20] = { 0x2a0, 0, 3 },
164 [PAD_GPIO21] = { 0x2a0, 3, 3 },
165 [PAD_GPIO22] = { 0x2a0, 6, 3 },
166 [PAD_GPIO23] = { 0x2a0, 9, 3 },
167 [PAD_GPIO24] = { 0x2a0, 12, 3 },
168 [PAD_GPIO25] = { 0x2a0, 15, 3 },
169 [PAD_GPIO26] = { 0x2a0, 18, 3 },
170 [PAD_GPIO27] = { 0x2a0, 21, 3 },
171 [PAD_GPIO28] = { 0x2a0, 24, 3 },
172 [PAD_GPIO29] = { 0x2a0, 27, 3 },
173
174 [PAD_GPIO30] = { 0x2a4, 0, 3 },
175 [PAD_GPIO31] = { 0x2a4, 3, 3 },
176 [PAD_GPIO32] = { 0x2a4, 6, 3 },
177 [PAD_GPIO33] = { 0x2a4, 9, 3 },
178 [PAD_GPIO34] = { 0x2a4, 12, 3 },
179 [PAD_GPIO35] = { 0x2a4, 15, 3 },
180 [PAD_GPIO36] = { 0x2a4, 17, 3 },
181 [PAD_GPIO37] = { 0x2a4, 20, 3 },
182 [PAD_GPIO38] = { 0x2a4, 23, 3 },
183 [PAD_GPIO39] = { 0x2a4, 26, 3 },
184 [PAD_GPIO40] = { 0x2a4, 29, 3 },
185
186 [PAD_GPIO41] = { 0x2a8, 0, 3 },
187 [PAD_GPIO42] = { 0x2a8, 3, 3 },
188 [PAD_GPIO43] = { 0x2a8, 6, 3 },
189 [PAD_GPIO44] = { 0x2a8, 9, 3 },
190 [PAD_GPIO45] = { 0x2a8, 12, 3 },
191 [PAD_GPIO46] = { 0x2a8, 15, 3 },
192 [PAD_GPIO47] = { 0x2a8, 18, 3 },
193 [PAD_GPIO48] = { 0x2a8, 21, 3 },
194 [PAD_GPIO49] = { 0x2a8, 24, 3 },
195 [PAD_GPIO50] = { 0x2a8, 27, 3 },
196 [PAD_GPIO51] = { 0x2a8, 30, 3 },
197
198 [PAD_GPIO52] = { 0x2ac, 0, 3 },
199 [PAD_GPIO53] = { 0x2ac, 2, 3 },
200 [PAD_GPIO54] = { 0x2ac, 4, 3 },
201 [PAD_GPIO55] = { 0x2ac, 6, 3 },
202 [PAD_GPIO56] = { 0x2ac, 9, 3 },
203 [PAD_GPIO57] = { 0x2ac, 12, 3 },
204 [PAD_GPIO58] = { 0x2ac, 15, 3 },
205 [PAD_GPIO59] = { 0x2ac, 18, 3 },
206 [PAD_GPIO60] = { 0x2ac, 21, 3 },
207 [PAD_GPIO61] = { 0x2ac, 24, 3 },
208 [PAD_GPIO62] = { 0x2ac, 27, 3 },
209 [PAD_GPIO63] = { 0x2ac, 30, 3 },
210
211 [PAD_GPIO6] = { 0x2b0, 0, 3 },
212 [PAD_GPIO7] = { 0x2b0, 2, 3 },
213 [PAD_GPIO8] = { 0x2b0, 5, 3 },
214 [PAD_GPIO9] = { 0x2b0, 8, 3 },
215};
216
217struct jh7110_vin_group_sel {
218 u16 offset;
219 u8 shift;
220 u8 group;
221};
222
223static const struct jh7110_vin_group_sel
224 jh7110_sys_vin_group_sel[ARRAY_SIZE(jh7110_sys_pins)] = {
225 [PAD_GPIO6] = { 0x2b4, 21, 0 },
226 [PAD_GPIO7] = { 0x2b4, 18, 0 },
227 [PAD_GPIO8] = { 0x2b4, 15, 0 },
228 [PAD_GPIO9] = { 0x2b0, 11, 0 },
229 [PAD_GPIO10] = { 0x2b0, 20, 0 },
230 [PAD_GPIO11] = { 0x2b0, 23, 0 },
231 [PAD_GPIO12] = { 0x2b0, 26, 0 },
232 [PAD_GPIO13] = { 0x2b0, 29, 0 },
233 [PAD_GPIO14] = { 0x2b4, 0, 0 },
234 [PAD_GPIO15] = { 0x2b4, 3, 0 },
235 [PAD_GPIO16] = { 0x2b4, 6, 0 },
236 [PAD_GPIO17] = { 0x2b4, 9, 0 },
237 [PAD_GPIO18] = { 0x2b4, 12, 0 },
238 [PAD_GPIO19] = { 0x2b0, 14, 0 },
239 [PAD_GPIO20] = { 0x2b0, 17, 0 },
240
241 [PAD_GPIO21] = { 0x2b4, 21, 1 },
242 [PAD_GPIO22] = { 0x2b4, 18, 1 },
243 [PAD_GPIO23] = { 0x2b4, 15, 1 },
244 [PAD_GPIO24] = { 0x2b0, 11, 1 },
245 [PAD_GPIO25] = { 0x2b0, 20, 1 },
246 [PAD_GPIO26] = { 0x2b0, 23, 1 },
247 [PAD_GPIO27] = { 0x2b0, 26, 1 },
248 [PAD_GPIO28] = { 0x2b0, 29, 1 },
249 [PAD_GPIO29] = { 0x2b4, 0, 1 },
250 [PAD_GPIO30] = { 0x2b4, 3, 1 },
251 [PAD_GPIO31] = { 0x2b4, 6, 1 },
252 [PAD_GPIO32] = { 0x2b4, 9, 1 },
253 [PAD_GPIO33] = { 0x2b4, 12, 1 },
254 [PAD_GPIO34] = { 0x2b0, 14, 1 },
255 [PAD_GPIO35] = { 0x2b0, 17, 1 },
256
257 [PAD_GPIO36] = { 0x2b4, 21, 2 },
258 [PAD_GPIO37] = { 0x2b4, 18, 2 },
259 [PAD_GPIO38] = { 0x2b4, 15, 2 },
260 [PAD_GPIO39] = { 0x2b0, 11, 2 },
261 [PAD_GPIO40] = { 0x2b0, 20, 2 },
262 [PAD_GPIO41] = { 0x2b0, 23, 2 },
263 [PAD_GPIO42] = { 0x2b0, 26, 2 },
264 [PAD_GPIO43] = { 0x2b0, 29, 2 },
265 [PAD_GPIO44] = { 0x2b4, 0, 2 },
266 [PAD_GPIO45] = { 0x2b4, 3, 2 },
267 [PAD_GPIO46] = { 0x2b4, 6, 2 },
268 [PAD_GPIO47] = { 0x2b4, 9, 2 },
269 [PAD_GPIO48] = { 0x2b4, 12, 2 },
270 [PAD_GPIO49] = { 0x2b0, 14, 2 },
271 [PAD_GPIO50] = { 0x2b0, 17, 2 },
272};
273
274static void jh7110_set_function(struct udevice *dev,
275 unsigned int pin, u32 func)
276{
277 const struct jh7110_func_sel *fs = &jh7110_sys_func_sel[pin];
278 struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
279 void __iomem *reg;
280 u32 mask;
281
282 if (!fs->offset)
283 return;
284
285 if (func > fs->max)
286 return;
287
288 reg = priv->base + fs->offset;
289 func = func << fs->shift;
290 mask = 0x3U << fs->shift;
291
292 func |= readl(reg) & ~mask;
293 writel(func, reg);
294}
295
296static void jh7110_set_vin_group(struct udevice *dev, unsigned int pin)
297{
298 const struct jh7110_vin_group_sel *gs =
299 &jh7110_sys_vin_group_sel[pin];
300 struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
301 void __iomem *reg;
302 u32 mask;
303 u32 grp;
304
305 if (!gs->offset)
306 return;
307
308 reg = priv->base + gs->offset;
309 grp = gs->group << gs->shift;
310 mask = 0x3U << gs->shift;
311
312 grp |= readl(reg) & ~mask;
313 writel(grp, reg);
314}
315
316static int jh7110_sys_set_one_pin_mux(struct udevice *dev, unsigned int pin,
317 unsigned int din, u32 dout, u32 doen, u32 func)
318{
319 struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
320
321 if (pin < priv->info->ngpios && func == 0)
322 starfive_set_gpiomux(dev, pin, din, dout, doen);
323
324 jh7110_set_function(dev, pin, func);
325
326 if (pin < priv->info->ngpios && func == 2)
327 jh7110_set_vin_group(dev, pin);
328
329 return 0;
330}
331
332static int jh7110_sys_get_padcfg_base(struct udevice *dev,
333 unsigned int pin)
334{
335 if (pin < PAD_GMAC1_MDC)
336 return SYS_GPO_PDA_0_74_CFG;
337 else if (pin > PAD_GMAC1_TXC && pin <= PAD_QSPI_DATA3)
338 return SYS_GPO_PDA_89_94_CFG;
339 else
340 return -1;
341}
342
343static void jh7110_sys_init_hw(struct udevice *dev)
344{
345 struct starfive_pinctrl_priv *priv = dev_get_priv(dev);
346
347 /* mask all GPIO interrupts */
348 writel(0U, priv->base + JH7110_SYS_GPIOIE0);
349 writel(0U, priv->base + JH7110_SYS_GPIOIE1);
350 /* clear edge interrupt flags */
351 writel(~0U, priv->base + JH7110_SYS_GPIOIC0);
352 writel(~0U, priv->base + JH7110_SYS_GPIOIC1);
353 /* enable GPIO interrupts */
354 writel(1U, priv->base + JH7110_SYS_GPIOEN);
355}
356
357const struct starfive_pinctrl_soc_info jh7110_sys_pinctrl_info = {
358 /* pin conf */
359 .set_one_pinmux = jh7110_sys_set_one_pin_mux,
360 .get_padcfg_base = jh7110_sys_get_padcfg_base,
361
362 /* gpio dout/doen/din/gpioinput register */
363 .dout_reg_base = JH7110_SYS_DOUT,
364 .dout_mask = GENMASK(6, 0),
365 .doen_reg_base = JH7110_SYS_DOEN,
366 .doen_mask = GENMASK(5, 0),
367 .gpi_reg_base = JH7110_SYS_GPI,
368 .gpi_mask = GENMASK(6, 0),
369 .gpioin_reg_base = JH7110_SYS_GPIOIN,
370
371 /* gpio */
372 .gpio_bank_name = "GPIO",
373 .ngpios = JH7110_SYS_NGPIO,
374 .gpio_init_hw = jh7110_sys_init_hw,
375};
376
377static int jh7110_sys_pinctrl_probe(struct udevice *dev)
378{
379 struct starfive_pinctrl_soc_info *info =
380 (struct starfive_pinctrl_soc_info *)dev_get_driver_data(dev);
381
382 return starfive_pinctrl_probe(dev, info);
383}
384
385static const struct udevice_id jh7110_sys_pinctrl_ids[] = {
386 /* JH7110 sys pinctrl */
387 { .compatible = "starfive,jh7110-sys-pinctrl",
388 .data = (ulong)&jh7110_sys_pinctrl_info, },
389 { /* sentinel */ }
390};
391
392U_BOOT_DRIVER(jh7110_sys_pinctrl) = {
393 .name = "jh7110-sys-pinctrl",
394 .id = UCLASS_PINCTRL,
395 .of_match = jh7110_sys_pinctrl_ids,
396 .priv_auto = sizeof(struct starfive_pinctrl_priv),
397 .ops = &starfive_pinctrl_ops,
398 .probe = jh7110_sys_pinctrl_probe,
399};