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Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +09001#ifndef __CONFIG_H
2#define __CONFIG_H
3
4#undef DEBUG
5
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +09006#define CONFIG_CPU_SH7751 1
7#define CONFIG_CPU_SH_TYPE_R 1
8#define CONFIG_R2DPLUS 1
9#define __LITTLE_ENDIAN__ 1
10
11/*
12 * Command line configuration.
13 */
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090014#define CONFIG_CMD_PCI
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090015#define CONFIG_CMD_IDE
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090016#define CONFIG_DOS_PARTITION
Nobuhiro Iwamatsu64ae5b92010-12-08 14:01:12 +090017#define CONFIG_CMD_SH_ZIMAGEBOOT
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090018
19/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6ce9ea62008-08-13 01:40:38 +020020#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090021#define CONFIG_BAUDRATE 115200
22#define CONFIG_CONS_SCIF1 1
Helmut Raigerd5a184b2011-10-20 04:19:47 +000023#define CONFIG_BOARD_LATE_INIT
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090024
25#define CONFIG_BOOTDELAY -1
26#define CONFIG_BOOTARGS "console=ttySC0,115200"
27#define CONFIG_ENV_OVERWRITE 1
28
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090029/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020030#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
31#define CONFIG_SYS_SDRAM_SIZE (0x04000000)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090032
Nobuhiro Iwamatsucda9c552011-01-17 20:48:39 +090033#define CONFIG_SYS_TEXT_BASE 0x0FFC0000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020034#define CONFIG_SYS_LONGHELP
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020035#define CONFIG_SYS_CBSIZE 256
36#define CONFIG_SYS_PBSIZE 256
37#define CONFIG_SYS_MAXARGS 16
38#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090039
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020040#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
Wolfgang Denk0708bc62010-10-07 21:51:12 +020041#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090042
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090044/* Address of u-boot image in Flash */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020045#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
46#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090047/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020049#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090050
51/*
Nobuhiro Iwamatsue0980752008-06-17 16:28:05 +090052 * NOR Flash ( Spantion S29GL256P )
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090053 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020054#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +020055#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020056#define CONFIG_SYS_FLASH_BASE (0xA0000000)
57#define CONFIG_SYS_MAX_FLASH_BANKS (1)
58#define CONFIG_SYS_MAX_FLASH_SECT 256
59#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090060
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +020061#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +020062#define CONFIG_ENV_SECT_SIZE 0x40000
63#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090065
66/*
67 * SuperH Clock setting
68 */
69#define CONFIG_SYS_CLK_FREQ 60000000
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +090070#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
71#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +020072#define CONFIG_SYS_TMU_CLK_DIV 4
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#define CONFIG_SYS_PLL_SETTLING_TIME 100/* in us */
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090074
75/*
76 * IDE support
77 */
78#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_PIO_MODE 1
80#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
81#define CONFIG_SYS_IDE_MAXDEVICE 1
82#define CONFIG_SYS_ATA_BASE_ADDR 0xb4000000
83#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
84#define CONFIG_SYS_ATA_DATA_OFFSET 0x1000 /* data reg offset */
85#define CONFIG_SYS_ATA_REG_OFFSET 0x1000 /* reg offset */
86#define CONFIG_SYS_ATA_ALT_OFFSET 0x800 /* alternate register offset */
Albert Aribaud036c6b42010-08-08 05:17:05 +053087#define CONFIG_IDE_SWAP_IO
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +090088
89/*
90 * SuperH PCI Bridge Configration
91 */
92#define CONFIG_PCI
93#define CONFIG_SH4_PCI
94#define CONFIG_SH7751_PCI
95#define CONFIG_PCI_PNP
96#define CONFIG_PCI_SCAN_SHOW 1
97#define __io
98#define __mem_pci
99
100#define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
101#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
102#define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
103#define CONFIG_PCI_IO_BUS 0xFE240000 /* IO space base address */
104#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
105#define CONFIG_PCI_IO_SIZE 0x00040000 /* Size of IO window */
Yoshihiro Shimoda6f9d7722009-02-25 16:04:26 +0900106#define CONFIG_PCI_SYS_BUS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
107#define CONFIG_PCI_SYS_PHYS (CONFIG_SYS_SDRAM_BASE & 0x1fffffff)
108#define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +0900109
Nobuhiro Iwamatsu868b52b2008-03-25 17:11:24 +0900110#endif /* __CONFIG_H */