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Asen Dimovddd0bda2010-04-20 22:49:04 +03001/*
2 * (C) Copyright 2010
3 * Ilko Iliev <iliev@ronetix.at>
4 * Asen Dimov <dimov@ronetix.at>
5 * Ronetix GmbH <www.ronetix.at>
6 *
7 * (C) Copyright 2007-2008
Stelian Pop5ee0c7f2011-11-01 00:00:39 +01008 * Stelian Pop <stelian@popies.net>
Asen Dimovddd0bda2010-04-20 22:49:04 +03009 * Lead Tech Design <www.leadtechdesign.com>
10 *
11 * Configuation settings for the PM9G45 board.
12 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +020013 * SPDX-License-Identifier: GPL-2.0+
Asen Dimovddd0bda2010-04-20 22:49:04 +030014 */
15
16#ifndef __CONFIG_H
17#define __CONFIG_H
18
Asen Dimova1e4e2b2011-06-08 22:01:37 +000019/*
20 * SoC must be defined first, before hardware.h is included.
21 * In this case SoC is defined in boards.cfg.
22 */
23#include <asm/hardware.h>
24
Asen Dimovddd0bda2010-04-20 22:49:04 +030025#define CONFIG_PM9G45 1 /* It's an Ronetix PM9G45 */
Asen Dimova1e4e2b2011-06-08 22:01:37 +000026#define CONFIG_SYS_AT91_CPU_NAME "AT91SAM9G45"
Asen Dimovddd0bda2010-04-20 22:49:04 +030027
Asen Dimov9fdb39b2011-10-31 08:54:20 +000028#define MACH_TYPE_PM9G45 2672
29#define CONFIG_MACH_TYPE MACH_TYPE_PM9G45
30
Asen Dimovddd0bda2010-04-20 22:49:04 +030031/* ARM asynchronous clock */
32#define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* from 12 MHz crystal */
Asen Dimova1e4e2b2011-06-08 22:01:37 +000033#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
Asen Dimova1e4e2b2011-06-08 22:01:37 +000034#define CONFIG_SYS_TEXT_BASE 0x73f00000
Asen Dimovddd0bda2010-04-20 22:49:04 +030035
36#define CONFIG_ARCH_CPU_INIT
37
38#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
39#define CONFIG_SETUP_MEMORY_TAGS 1
40#define CONFIG_INITRD_TAG 1
41
42#define CONFIG_SKIP_LOWLEVEL_INIT
Asen Dimova04fad92011-12-09 11:00:07 +000043#define CONFIG_BOARD_EARLY_INIT_F
Asen Dimovddd0bda2010-04-20 22:49:04 +030044
45/*
46 * Hardware drivers
47 */
48#define CONFIG_AT91_GPIO 1
49#define CONFIG_ATMEL_USART 1
Asen Dimova1e4e2b2011-06-08 22:01:37 +000050#define CONFIG_USART_BASE ATMEL_BASE_DBGU
51#define CONFIG_USART_ID ATMEL_ID_SYS
Asen Dimovddd0bda2010-04-20 22:49:04 +030052
53#define CONFIG_SYS_USE_NANDFLASH 1
54
55/* LED */
56#define CONFIG_AT91_LED
Andreas Bießmann30263a22013-11-29 12:13:46 +010057#define CONFIG_RED_LED GPIO_PIN_PD(31) /* this is the user1 led */
58#define CONFIG_GREEN_LED GPIO_PIN_PD(0) /* this is the user2 led */
Asen Dimovddd0bda2010-04-20 22:49:04 +030059
60#define CONFIG_BOOTDELAY 3
61
62/*
63 * BOOTP options
64 */
65#define CONFIG_BOOTP_BOOTFILESIZE 1
66#define CONFIG_BOOTP_BOOTPATH 1
67#define CONFIG_BOOTP_GATEWAY 1
68#define CONFIG_BOOTP_HOSTNAME 1
69
70/*
71 * Command line configuration.
72 */
Asen Dimovddd0bda2010-04-20 22:49:04 +030073#define CONFIG_CMD_NAND 1
Asen Dimovddd0bda2010-04-20 22:49:04 +030074
75#define CONFIG_CMD_JFFS2 1
76#define CONFIG_JFFS2_CMDLINE 1
77#define CONFIG_JFFS2_NAND 1
78#define CONFIG_JFFS2_DEV "nand0" /* NAND dev jffs2 lives on */
79#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */
80#define CONFIG_JFFS2_PART_SIZE (256 * 1024 * 1024) /* partition */
81
82/* SDRAM */
83#define CONFIG_NR_DRAM_BANKS 1
84#define PHYS_SDRAM 0x70000000
85#define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */
86
87/* NOR flash, not available */
88#define CONFIG_SYS_NO_FLASH 1
Asen Dimovddd0bda2010-04-20 22:49:04 +030089
90/* NAND flash */
91#ifdef CONFIG_CMD_NAND
Asen Dimovddd0bda2010-04-20 22:49:04 +030092#define CONFIG_NAND_ATMEL
93#define CONFIG_SYS_MAX_NAND_DEVICE 1
94#define CONFIG_SYS_NAND_BASE 0x40000000
95#define CONFIG_SYS_NAND_DBW_8 1
96/* our ALE is AD21 */
97#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
98/* our CLE is AD22 */
99#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
Andreas Bießmanna4c24d32013-11-29 12:13:45 +0100100#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
101#define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(3)
Asen Dimovddd0bda2010-04-20 22:49:04 +0300102
103#endif
104
105/* Ethernet */
106#define CONFIG_MACB 1
107#define CONFIG_RMII 1
Asen Dimovddd0bda2010-04-20 22:49:04 +0300108#define CONFIG_NET_RETRY_COUNT 20
109#define CONFIG_RESET_PHY_R 1
110
111/* USB */
112#define CONFIG_USB_ATMEL
Bo Shen4a985df2013-10-21 16:14:00 +0800113#define CONFIG_USB_ATMEL_CLK_SEL_UPLL
Asen Dimovddd0bda2010-04-20 22:49:04 +0300114#define CONFIG_USB_OHCI_NEW 1
115#define CONFIG_DOS_PARTITION 1
116#define CONFIG_SYS_USB_OHCI_CPU_INIT 1
117#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00700000 /* _UHP_OHCI_BASE */
118#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9g45"
119#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
120#define CONFIG_USB_STORAGE 1
121
122/* board specific(not enough SRAM) */
123#define CONFIG_AT91SAM9G45_LCD_BASE PHYS_SDRAM + 0xE00000
124
125#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM + 0x2000000 /* load addr */
126
127#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM
128#define CONFIG_SYS_MEMTEST_END CONFIG_AT91SAM9G45_LCD_BASE
129
130/* bootstrap + u-boot + env + linux in nandflash */
131#define CONFIG_ENV_IS_IN_NAND 1
132#define CONFIG_ENV_OFFSET 0x60000
133#define CONFIG_ENV_OFFSET_REDUND 0x80000
134#define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */
135#define CONFIG_BOOTCOMMAND "nand read 0x72000000 0x200000 0x200000; bootm"
136#define CONFIG_BOOTARGS "fbcon=rotate:3 console=tty0 " \
137 "console=ttyS0,115200 " \
138 "root=/dev/mtdblock4 " \
139 "mtdparts=atmel_nand:128k(bootstrap)ro," \
140 "256k(uboot)ro,1664k(env)," \
141 "2M(linux)ro,-(root) rw " \
142 "rootfstype=jffs2"
143
144#define CONFIG_BAUDRATE 115200
Asen Dimovddd0bda2010-04-20 22:49:04 +0300145
Asen Dimovddd0bda2010-04-20 22:49:04 +0300146#define CONFIG_SYS_CBSIZE 256
147#define CONFIG_SYS_MAXARGS 16
148#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
149 sizeof(CONFIG_SYS_PROMPT) + 16)
150#define CONFIG_SYS_LONGHELP 1
151#define CONFIG_CMDLINE_EDITING 1
152#define CONFIG_AUTO_COMPLETE
Asen Dimovddd0bda2010-04-20 22:49:04 +0300153
154/*
155 * Size of malloc() pool
156 */
157#define CONFIG_SYS_MALLOC_LEN ROUND(3 * CONFIG_ENV_SIZE + 128*1024,\
158 0x1000)
Asen Dimovddd0bda2010-04-20 22:49:04 +0300159
Asen Dimov8322d4e2010-12-12 00:42:28 +0000160#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
161#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
162 GENERATED_GBL_DATA_SIZE)
163
Asen Dimovddd0bda2010-04-20 22:49:04 +0300164#endif