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Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +09001/*
2 * Configuation settings for the Renesas Solutions AP-325RXA board
3 *
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 * Copyright (C) 2008 Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
6 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +09008 */
9
10#ifndef __AP325RXA_H
11#define __AP325RXA_H
12
13#undef DEBUG
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090014#define CONFIG_CPU_SH7723 1
15#define CONFIG_AP325RXA 1
16
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090017#define CONFIG_CMD_SDRAM
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090018#define CONFIG_CMD_IDE
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090019#define CONFIG_DOS_PARTITION
20
21#define CONFIG_BAUDRATE 38400
22#define CONFIG_BOOTDELAY 3
23#define CONFIG_BOOTARGS "console=ttySC2,38400"
24
25#define CONFIG_VERSION_VARIABLE
26#undef CONFIG_SHOW_BOOT_PROGRESS
27
28/* SMC9118 */
Ben Warrenfbfdd3a2009-07-20 22:01:11 -070029#define CONFIG_SMC911X 1
30#define CONFIG_SMC911X_32_BIT 1
31#define CONFIG_SMC911X_BASE 0xB6080000
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090032
33/* MEMORY */
34#define AP325RXA_SDRAM_BASE (0x88000000)
35#define AP325RXA_FLASH_BASE_1 (0xA0000000)
36#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024)
37
Nobuhiro Iwamatsuf9386d52011-01-17 20:46:35 +090038#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
39
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090040/* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020041#define CONFIG_SYS_LONGHELP
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090042/* Monitor Command Prompt */
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090043/* Buffer size for input from the Console */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020044#define CONFIG_SYS_CBSIZE 256
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090045/* Buffer size for Console output */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046#define CONFIG_SYS_PBSIZE 256
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090047/* max args accepted for monitor commands */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020048#define CONFIG_SYS_MAXARGS 16
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090049/* Buffer size for Boot Arguments passed to kernel */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020050#define CONFIG_SYS_BARGSIZE 512
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090051/* List of legal baudrate settings for this board */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020052#define CONFIG_SYS_BAUDRATE_TABLE { 38400 }
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090053
54/* SCIF */
55#define CONFIG_SCIF_CONSOLE 1
56#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */
57#define CONFIG_CONS_SCIF5 1
58
59/* Suppress display of console information at boot */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020060#undef CONFIG_SYS_CONSOLE_INFO_QUIET
61#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
62#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090063
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020064#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE)
65#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090066
67/* Enable alternate, more extensive, memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020068#undef CONFIG_SYS_ALT_MEMTEST
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090069/* Scratch address used by the alternate memory test */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#undef CONFIG_SYS_MEMTEST_SCRATCH
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090071
72/* Enable temporary baudrate change while serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020073#undef CONFIG_SYS_LOADS_BAUD_CHANGE
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090074
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020075#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090076/* maybe more, but if so u-boot doesn't know about it... */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090078/* default load address for scripts ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090080
81/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020082#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090083/* Monitor size */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020084#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090085/* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020086#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020087#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090088
89/* FLASH */
90#define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020091#define CONFIG_SYS_FLASH_CFI
92#undef CONFIG_SYS_FLASH_QUIET_TEST
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090093/* print 'E' for empty sector on flinfo */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020094#define CONFIG_SYS_FLASH_EMPTY_INFO
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090095/* Physical start address of Flash memory */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020096#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090097/* Max number of sectors on each Flash chip */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020098#define CONFIG_SYS_MAX_FLASH_SECT 512
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +090099
100/*
101 * IDE support
102 */
103#define CONFIG_IDE_RESET 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200104#define CONFIG_SYS_PIO_MODE 1
105#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */
106#define CONFIG_SYS_IDE_MAXDEVICE 1
107#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000
108#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */
109#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */
110#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */
111#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */
Albert Aribaud036c6b42010-08-08 05:17:05 +0530112#define CONFIG_IDE_SWAP_IO
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900113
114/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200115#define CONFIG_SYS_MAX_FLASH_BANKS 1
116#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)}
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900117
118/* Timeout for Flash erase operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200119#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900120/* Timeout for Flash write operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200121#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900122/* Timeout for Flash set sector lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200123#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900124/* Timeout for Flash clear lock bit operations (in ms) */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200125#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900126
127/*
128 * Use hardware flash sectors protection instead
129 * of U-Boot software protection
130 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200131#undef CONFIG_SYS_FLASH_PROTECTION
132#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900133
134/* ENV setting */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200135#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900136#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200137#define CONFIG_ENV_SECT_SIZE (128 * 1024)
138#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
140/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
141#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200142#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900143
144/* Board Clock */
145#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsue6984492013-08-21 16:11:21 +0900146#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
147#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARD32e6acc2009-06-04 12:06:48 +0200148#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu3e590432008-08-22 17:39:09 +0900149
150#endif /* __AP325RXA_H */