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git01.mediatek.com / filogic / uboot / 151b9350820861f4323cef01f415f0b29f575bcc / . / arch / x86 / dts / chromebook_samus.dts
blob: 5dd3e57cb9bfc0a0b754bd7e77d8aabbac2dd222 [file] [log] [blame]
Simon Glassa0b09612016-03-16 07:44:43 -0600[diff] [blame]1/dts-v1/;
2
3#include <dt-bindings/gpio/x86-gpio.h>
4
5/include/ "skeleton.dtsi"
6/include/ "keyboard.dtsi"
7/include/ "serial.dtsi"
8/include/ "rtc.dtsi"
9/include/ "tsc_timer.dtsi"
10
11/ {
12 model = "Google Samus";
13 compatible = "google,samus", "intel,broadwell";
14
15 aliases {
16 spi0 = &spi;
17 usb0 = &usb_0;
18 usb1 = &usb_1;
19 };
20
21 config {
22 silent_console = <0>;
23 };
24
25 cpus {
26 #address-cells = <1>;
27 #size-cells = <0>;
28
29 cpu@0 {
30 device_type = "cpu";
31 compatible = "intel,core-i3-gen5";
32 reg = <0>;
33 intel,apic-id = <0>;
34 intel,slow-ramp = <3>;
35 };
36
37 cpu@1 {
38 device_type = "cpu";
39 compatible = "intel,core-i3-gen5";
40 reg = <1>;
41 intel,apic-id = <1>;
42 };
43
44 cpu@2 {
45 device_type = "cpu";
46 compatible = "intel,core-i3-gen5";
47 reg = <2>;
48 intel,apic-id = <2>;
49 };
50
51 cpu@3 {
52 device_type = "cpu";
53 compatible = "intel,core-i3-gen5";
54 reg = <3>;
55 intel,apic-id = <3>;
56 };
57
58 };
59
60 chosen {
61 stdout-path = "/serial";
62 };
63
64 keyboard {
65 intel,duplicate-por;
66 };
67
68 pch_pinctrl {
69 compatible = "intel,x86-broadwell-pinctrl";
70 u-boot,dm-pre-reloc;
71 reg = <0 0>;
72
73 /* Put this first: it is the default */
74 gpio_unused: gpio-unused {
75 mode-gpio;
76 direction = <PIN_INPUT>;
77 owner = <OWNER_GPIO>;
78 sense-disable;
79 };
80
81 gpio_acpi_sci: acpi-sci {
82 mode-gpio;
83 direction = <PIN_INPUT>;
84 invert;
85 route = <ROUTE_SCI>;
86 };
87
88 gpio_acpi_smi: acpi-smi {
89 mode-gpio;
90 direction = <PIN_INPUT>;
91 invert;
92 route = <ROUTE_SMI>;
93 };
94
95 gpio_input: gpio-input {
96 mode-gpio;
97 direction = <PIN_INPUT>;
98 owner = <OWNER_GPIO>;
99 };
100
101 gpio_input_invert: gpio-input-invert {
102 mode-gpio;
103 direction = <PIN_INPUT>;
104 owner = <OWNER_GPIO>;
105 invert;
106 };
107
108 gpio_native: gpio-native {
109 };
110
111 gpio_out_high: gpio-out-high {
112 mode-gpio;
113 direction = <PIN_OUTPUT>;
114 output-value = <1>;
115 owner = <OWNER_GPIO>;
116 sense-disable;
117 };
118
119 gpio_out_low: gpio-out-low {
120 mode-gpio;
121 direction = <PIN_OUTPUT>;
122 output-value = <0>;
123 owner = <OWNER_GPIO>;
124 sense-disable;
125 };
126
127 gpio_pirq: gpio-pirq {
128 mode-gpio;
129 direction = <PIN_INPUT>;
130 owner = <OWNER_GPIO>;
131 pirq-apic = <PIRQ_APIC_ROUTE>;
132 };
133
134 soc_gpio@0 {
135 config =
136 <0 &gpio_unused 0>, /* unused */
137 <1 &gpio_unused 0>, /* unused */
138 <2 &gpio_unused 0>, /* unused */
139 <3 &gpio_unused 0>, /* unused */
140 <4 &gpio_native 0>, /* native: i2c0_sda_gpio4 */
141 <5 &gpio_native 0>, /* native: i2c0_scl_gpio5 */
142 <6 &gpio_native 0>, /* native: i2c1_sda_gpio6 */
143 <7 &gpio_native 0>, /* native: i2c1_scl_gpio7 */
144 <8 &gpio_acpi_sci 0>, /* pch_lte_wake_l */
145 <9 &gpio_input_invert 0>, /* trackpad_int_l (wake) */
146 <10 &gpio_acpi_sci 0>, /* pch_wlan_wake_l */
147 <11 &gpio_unused 0>, /* unused */
148 <12 &gpio_unused 0>, /* unused */
149 <13 &gpio_pirq 3>, /* trackpad_int_l (pirql) */
150 <14 &gpio_pirq 4>, /* touch_int_l (pirqm) */
151 <15 &gpio_unused 0>, /* unused (strap) */
152 <16 &gpio_input 0>, /* pch_wp */
153 <17 &gpio_unused 0>, /* unused */
154 <18 &gpio_unused 0>, /* unused */
155 <19 &gpio_unused 0>, /* unused */
156 <20 &gpio_native 0>, /* pcie_wlan_clkreq_l */
157 <21 &gpio_out_high 0>, /* pp3300_ssd_en */
158 <22 &gpio_unused 0>, /* unused */
159 <23 &gpio_out_low 0>, /* pp3300_autobahn_en */
160 <24 &gpio_unused 0>, /* unused */
161 <25 &gpio_input 0>, /* ec_in_rw */
162 <26 &gpio_unused 0>, /* unused */
163 <27 &gpio_acpi_sci 0>, /* pch_wake_l */
164 <28 &gpio_unused 0>, /* unused */
165 <29 &gpio_unused 0>, /* unused */
166 <30 &gpio_native 0>, /* native: pch_suswarn_l */
167 <31 &gpio_native 0>, /* native: acok_buf */
168 <32 &gpio_native 0>, /* native: lpc_clkrun_l */
169 <33 &gpio_native 0>, /* native: ssd_devslp */
170 <34 &gpio_acpi_smi 0>, /* ec_smi_l */
171 <35 &gpio_acpi_smi 0>, /* pch_nmi_dbg_l (route in nmi_en) */
172 <36 &gpio_acpi_sci 0>, /* ec_sci_l */
173 <37 &gpio_unused 0>, /* unused */
174 <38 &gpio_unused 0>, /* unused */
175 <39 &gpio_unused 0>, /* unused */
176 <40 &gpio_native 0>, /* native: pch_usb1_oc_l */
177 <41 &gpio_native 0>, /* native: pch_usb2_oc_l */
178 <42 &gpio_unused 0>, /* wlan_disable_l */
179 <43 &gpio_out_high 0>, /* pp1800_codec_en */
180 <44 &gpio_unused 0>, /* unused */
181 <45 &gpio_acpi_sci 0>, /* dsp_int - codec wake */
182 <46 &gpio_pirq 6>, /* hotword_det_l_3v3 (pirqo) - codec irq */
183 <47 &gpio_out_low 0>, /* ssd_reset_l */
184 <48 &gpio_unused 0>, /* unused */
185 <49 &gpio_unused 0>, /* unused */
186 <50 &gpio_unused 0>, /* unused */
187 <51 &gpio_unused 0>, /* unused */
188 <52 &gpio_input 0>, /* sim_det */
189 <53 &gpio_unused 0>, /* unused */
190 <54 &gpio_unused 0>, /* unused */
191 <55 &gpio_unused 0>, /* unused */
192 <56 &gpio_unused 0>, /* unused */
193 <57 &gpio_out_high 0>, /* codec_reset_l */
194 <58 &gpio_unused 0>, /* unused */
195 <59 &gpio_out_high 0>, /* lte_disable_l */
196 <60 &gpio_unused 0>, /* unused */
197 <61 &gpio_native 0>, /* native: pch_sus_stat */
198 <62 &gpio_native 0>, /* native: pch_susclk */
199 <63 &gpio_native 0>, /* native: pch_slp_s5_l */
200 <64 &gpio_unused 0>, /* unused */
201 <65 &gpio_input 0>, /* ram_id3 */
202 <66 &gpio_input 0>, /* ram_id3_old (strap) */
203 <67 &gpio_input 0>, /* ram_id0 */
204 <68 &gpio_input 0>, /* ram_id1 */
205 <69 &gpio_input 0>, /* ram_id2 */
206 <70 &gpio_unused 0>, /* unused */
207 <71 &gpio_native 0>, /* native: modphy_en */
208 <72 &gpio_unused 0>, /* unused */
209 <73 &gpio_unused 0>, /* unused */
210 <74 &gpio_unused 0>, /* unused */
211 <75 &gpio_unused 0>, /* unused */
212 <76 &gpio_unused 0>, /* unused */
213 <77 &gpio_unused 0>, /* unused */
214 <78 &gpio_unused 0>, /* unused */
215 <79 &gpio_unused 0>, /* unused */
216 <80 &gpio_unused 0>, /* unused */
217 <81 &gpio_unused 0>, /* unused */
218 <82 &gpio_native 0>, /* native: ec_rcin_l */
219 <83 &gpio_native 0>, /* gspi0_cs */
220 <84 &gpio_native 0>, /* gspi0_clk */
221 <85 &gpio_native 0>, /* gspi0_miso */
222 <86 &gpio_native 0>, /* gspi0_mosi (strap) */
223 <87 &gpio_unused 0>, /* unused */
224 <88 &gpio_unused 0>, /* unused */
225 <89 &gpio_out_high 0>, /* pp3300_sd_en */
226 <90 &gpio_unused 0>, /* unused */
227 <91 &gpio_unused 0>, /* unused */
228 <92 &gpio_unused 0>, /* unused */
229 <93 &gpio_unused 0>, /* unused */
230 <94 &gpio_unused 0>; /* unused */
231 };
232 };
233
234 pci {
235 compatible = "pci-x86";
236 #address-cells = <3>;
237 #size-cells = <2>;
238 u-boot,dm-pre-reloc;
239 ranges = <0x02000000 0x0 0xe0000000 0xe0000000 0 0x10000000
240 0x42000000 0x0 0xd0000000 0xd0000000 0 0x10000000
241 0x01000000 0x0 0x1000 0x1000 0 0xefff>;
242
243 northbridge@0,0 {
244 reg = <0x00000000 0 0 0 0>;
245 compatible = "intel,broadwell-northbridge";
246 board-id-gpios = <&gpio_c 5 0>, <&gpio_c 4 0>,
247 <&gpio_c 3 0>, <&gpio_c 1 0>;
248 u-boot,dm-pre-reloc;
249 spd {
250 #address-cells = <1>;
251 #size-cells = <0>;
252 samsung_4 {
253 reg = <6>;
254 data = [91 20 f1 03 04 11 05 0b
255 03 11 01 08 0a 00 50 01
256 78 78 90 50 90 11 50 e0
257 10 04 3c 3c 01 90 00 00
258 00 80 00 00 00 00 00 a8
259 00 00 00 00 00 00 00 00
260 00 00 00 00 00 00 00 00
261 00 00 00 00 0f 11 02 00
262 00 00 00 00 00 00 00 00
263 00 00 00 00 00 00 00 00
264 00 00 00 00 00 00 00 00
265 00 00 00 00 00 00 00 00
266 00 00 00 00 00 00 00 00
267 00 00 00 00 00 00 00 00
268 00 00 00 00 00 80 ce 01
269 00 00 55 00 00 00 00 00
270 4b 34 45 38 45 33 30 34
271 45 44 2d 45 47 43 45 20
272 20 20 00 00 80 ce 00 00
273 00 00 00 00 00 00 00 00
274 00 00 00 00 00 00 00 00
275 00 00 00 00 00 00 00 00
276 00 00 00 00 00 00 00 00
277 00 00 00 00 00 00 00 00
278 00 00 00 00 00 00 00 00
279 00 00 00 00 00 00 00 00
280 00 00 00 00 00 00 00 00
281 00 00 00 00 00 00 00 00
282 00 00 00 00 00 00 00 00
283 00 00 00 00 00 00 00 00
284 00 00 00 00 00 00 00 00
285 00 00 00 00 00 00 00 00];
286 };
287 hynix-h9ccnnnbltmlar-ntm-lpddr3-32 {
288 /*
289 * banks 8, ranks 2, rows 14,
290 * columns 10, density 4096 mb, x32
291 */
292 reg = <8>;
293 data = [91 20 f1 03 04 11 05 0b
294 03 11 01 08 0a 00 50 01
295 78 78 90 50 90 11 50 e0
296 10 04 3c 3c 01 90 00 00
297 00 80 00 00 00 00 00 a8
298 00 00 00 00 00 00 00 00
299 00 00 00 00 00 00 00 00
300 00 00 00 00 0f 01 02 00
301 00 00 00 00 00 00 00 00
302 00 00 00 00 00 00 00 00
303 00 00 00 00 00 00 00 00
304 00 00 00 00 00 00 00 00
305 00 00 00 00 00 00 00 00
306 00 00 00 00 00 00 00 00
307 00 00 00 00 00 80 ad 00
308 00 00 55 00 00 00 00 00
309 48 39 43 43 4e 4e 4e 42
310 4c 54 4d 4c 41 52 2d 4e
311 54 4d 00 00 80 ad 00 00
312 00 00 00 00 00 00 00 00
313 00 00 00 00 00 00 00 00
314 00 00 00 00 00 00 00 00
315 00 00 00 00 00 00 00 00
316 00 00 00 00 00 00 00 00
317 00 00 00 00 00 00 00 00
318 00 00 00 00 00 00 00 00
319 00 00 00 00 00 00 00 00
320 00 00 00 00 00 00 00 00
321 00 00 00 00 00 00 00 00
322 00 00 00 00 00 00 00 00
323 00 00 00 00 00 00 00 00
324 00 00 00 00 00 00 00 00];
325 };
326 samsung_8 {
327 reg = <10>;
328 data = [91 20 f1 03 04 12 05 0a
329 03 11 01 08 0a 00 50 01
330 78 78 90 50 90 11 50 e0
331 10 04 3c 3c 01 90 00 00
332 00 80 00 00 00 00 00 a8
333 00 00 00 00 00 00 00 00
334 00 00 00 00 00 00 00 00
335 00 00 00 00 0f 11 02 00
336 00 00 00 00 00 00 00 00
337 00 00 00 00 00 00 00 00
338 00 00 00 00 00 00 00 00
339 00 00 00 00 00 00 00 00
340 00 00 00 00 00 00 00 00
341 00 00 00 00 00 00 00 00
342 00 00 00 00 00 80 ce 01
343 00 00 55 00 00 00 00 00
344 4b 34 45 36 45 33 30 34
345 45 44 2d 45 47 43 45 20
346 20 20 00 00 80 ce 00 00
347 00 00 00 00 00 00 00 00
348 00 00 00 00 00 00 00 00
349 00 00 00 00 00 00 00 00
350 00 00 00 00 00 00 00 00
351 00 00 00 00 00 00 00 00
352 00 00 00 00 00 00 00 00
353 00 00 00 00 00 00 00 00
354 00 00 00 00 00 00 00 00
355 00 00 00 00 00 00 00 00
356 00 00 00 00 00 00 00 00
357 00 00 00 00 00 00 00 00
358 00 00 00 00 00 00 00 00
359 00 00 00 00 00 00 00 00];
360 };
361 hynix-h9ccnnnbltmlar-ntm-lpddr3-16 {
362 /*
363 * banks 8, ranks 2, rows 14,
364 * columns 11, density 4096 mb, x16
365 */
366 reg = <12>;
367 data = [91 20 f1 03 04 12 05 0a
368 03 11 01 08 0a 00 50 01
369 78 78 90 50 90 11 50 e0
370 10 04 3c 3c 01 90 00 00
371 00 80 00 00 00 00 00 a8
372 00 00 00 00 00 00 00 00
373 00 00 00 00 00 00 00 00
374 00 00 00 00 0f 01 02 00
375 00 00 00 00 00 00 00 00
376 00 00 00 00 00 00 00 00
377 00 00 00 00 00 00 00 00
378 00 00 00 00 00 00 00 00
379 00 00 00 00 00 00 00 00
380 00 00 00 00 00 00 00 00
381 00 00 00 00 00 80 ad 00
382 00 00 55 00 00 00 00 00
383 48 39 43 43 4e 4e 4e 42
384 4c 54 4d 4c 41 52 2d 4e
385 54 4d 00 00 80 ad 00 00
386 00 00 00 00 00 00 00 00
387 00 00 00 00 00 00 00 00
388 00 00 00 00 00 00 00 00
389 00 00 00 00 00 00 00 00
390 00 00 00 00 00 00 00 00
391 00 00 00 00 00 00 00 00
392 00 00 00 00 00 00 00 00
393 00 00 00 00 00 00 00 00
394 00 00 00 00 00 00 00 00
395 00 00 00 00 00 00 00 00
396 00 00 00 00 00 00 00 00
397 00 00 00 00 00 00 00 00
398 00 00 00 00 00 00 00 00];
399 };
400 hynix-h9ccnnncltmlar-lpddr3 {
401 /*
402 * banks 8, ranks 2, rows 15,
403 * columns 11, density 8192 mb, x16
404 */
405 reg = <13>;
406 data = [91 20 f1 03 05 1a 05 0a
407 03 11 01 08 0a 00 50 01
408 78 78 90 50 90 11 50 e0
409 90 06 3c 3c 01 90 00 00
410 00 80 00 00 00 00 00 a8
411 00 00 00 00 00 00 00 00
412 00 00 00 00 00 00 00 00
413 00 00 00 00 0f 01 02 00
414 00 00 00 00 00 00 00 00
415 00 00 00 00 00 00 00 00
416 00 00 00 00 00 00 00 00
417 00 00 00 00 00 00 00 00
418 00 00 00 00 00 00 00 00
419 00 00 00 00 00 00 00 00
420 00 00 00 00 00 80 ad 00
421 00 00 55 00 00 00 00 00
422 48 39 43 43 4e 4e 4e 43
423 4c 54 4d 4c 41 52 00 00
424 00 00 00 00 80 ad 00 00
425 00 00 00 00 00 00 00 00
426 00 00 00 00 00 00 00 00
427 00 00 00 00 00 00 00 00
428 00 00 00 00 00 00 00 00
429 00 00 00 00 00 00 00 00
430 00 00 00 00 00 00 00 00
431 00 00 00 00 00 00 00 00
432 00 00 00 00 00 00 00 00
433 00 00 00 00 00 00 00 00
434 00 00 00 00 00 00 00 00
435 00 00 00 00 00 00 00 00
436 00 00 00 00 00 00 00 00
437 00 00 00 00 00 00 00 00];
438 };
439 elpida-edfb232a1ma {
440 /*
441 * banks 8, ranks 2, rows 15,
442 * columns 11, density 8192 mb, x16
443 */
444 reg = <15>;
445 data = [91 20 f1 03 05 1a 05 0a
446 03 11 01 08 0a 00 50 01
447 78 78 90 50 90 11 50 e0
448 90 06 3c 3c 01 90 00 00
449 00 80 00 00 00 00 00 a8
450 00 00 00 00 00 00 00 00
451 00 00 00 00 00 00 00 00
452 00 00 00 00 0f 01 02 00
453 00 00 00 00 00 00 00 00
454 00 00 00 00 00 00 00 00
455 00 00 00 00 00 00 00 00
456 00 00 00 00 00 00 00 00
457 00 00 00 00 00 00 00 00
458 00 00 00 00 00 00 00 00
459 00 00 00 00 00 02 fe 00
460 00 00 00 00 00 00 00 00
461 45 44 46 42 32 33 32 41
462 31 4d 41 2d 47 44 2d 46
463 00 00 00 00 02 fe 00 00
464 00 00 00 00 00 00 00 00
465 00 00 00 00 00 00 00 00
466 00 00 00 00 00 00 00 00
467 00 00 00 00 00 00 00 00
468 00 00 00 00 00 00 00 00
469 00 00 00 00 00 00 00 00
470 00 00 00 00 00 00 00 00
471 00 00 00 00 00 00 00 00
472 00 00 00 00 00 00 00 00
473 00 00 00 00 00 00 00 00
474 00 00 00 00 00 00 00 00
475 00 00 00 00 00 00 00 00
476 00 00 00 00 00 00 00 00];
477 };
478 };
479 };
480
481 gma@2,0 {
482 reg = <0x00001000 0 0 0 0>;
483 compatible = "intel,broadwell-igd";
484 intel,dp-hotplug = <6 6 6>;
485 intel,port-select = <1>; /* eDP */
486 intel,power-cycle-delay = <6>;
487 intel,power-up-delay = <2000>;
488 intel,power-down-delay = <500>;
489 intel,power-backlight-on-delay = <2000>;
490 intel,power-backlight-off-delay = <2000>;
491 intel,cpu-backlight = <0x00000200>;
492 intel,pch-backlight = <0x04000200>;
493 intel,pre-graphics-delay = <200>;
494 };
495
496 me@16,0 {
497 reg = <0x0000b000 0 0 0 0>;
498 compatible = "intel,me";
499 u-boot,dm-pre-reloc;
500 };
501
502 usb_1: usb@14,0 {
503 reg = <0x0000a000 0 0 0 0>;
504 compatible = "xhci-pci";
505 };
506
507 usb_0: usb@1d,0 {
508 status = "disabled";
509 reg = <0x0000e800 0 0 0 0>;
510 compatible = "ehci-pci";
511 };
512
513 pch@1f,0 {
514 reg = <0x0000f800 0 0 0 0>;
515 compatible = "intel,broadwell-pch";
516 u-boot,dm-pre-reloc;
517 #address-cells = <1>;
518 #size-cells = <1>;
519 intel,pirq-routing = <0x8b 0x8a 0x8b 0x8b
520 0x80 0x80 0x80 0x80>;
521 intel,gpi-routing = <0 0 0 0 0 0 0 2
522 1 0 0 0 0 0 0 0>;
523 /* Enable EC SMI source */
524 intel,alt-gp-smi-enable = <0x0040>;
525
526 /* EC-SCI is GPIO36 */
527 intel,gpe0-en = <0 0x10 0 0>;
528
529 power-enable-gpio = <&gpio_a 23 0>;
530
531 spi: spi {
532 #address-cells = <1>;
533 #size-cells = <0>;
534 compatible = "intel,ich9-spi";
535 spi-flash@0 {
536 #size-cells = <1>;
537 #address-cells = <1>;
538 reg = <0>;
539 compatible = "winbond,w25q64",
540 "spi-flash";
541 memory-map = <0xff800000 0x00800000>;
542 rw-mrc-cache {
543 label = "rw-mrc-cache";
544 reg = <0x003e0000 0x00010000>;
545 };
546 };
547 };
548
549 gpio_a: gpioa {
550 compatible = "intel,broadwell-gpio";
551 u-boot,dm-pre-reloc;
552 #gpio-cells = <2>;
553 gpio-controller;
554 reg = <0 0>;
555 bank-name = "A";
556 };
557
558 gpio_b: gpiob {
559 compatible = "intel,broadwell-gpio";
560 u-boot,dm-pre-reloc;
561 #gpio-cells = <2>;
562 gpio-controller;
563 reg = <1 0>;
564 bank-name = "B";
565 };
566
567 gpio_c: gpioc {
568 compatible = "intel,broadwell-gpio";
569 u-boot,dm-pre-reloc;
570 #gpio-cells = <2>;
571 gpio-controller;
572 reg = <2 0>;
573 bank-name = "C";
574 };
575
576 lpc {
577 compatible = "intel,broadwell-lpc";
578 #address-cells = <1>;
579 #size-cells = <0>;
580 u-boot,dm-pre-reloc;
581 intel,gen-dec = <0x800 0xfc 0x900 0xfc>;
582 cros-ec@200 {
583 compatible = "google,cros-ec-lpc";
584 reg = <0x204 1 0x200 1 0x880 0x80>;
585
586 /*
587 * Describes the flash memory within
588 * the EC
589 */
590 #address-cells = <1>;
591 #size-cells = <1>;
592 flash@8000000 {
593 reg = <0x08000000 0x20000>;
594 erase-value = <0xff>;
595 };
596 };
597 };
598 };
599
600 sata@1f,2 {
601 compatible = "intel,wildcatpoint-ahci";
602 reg = <0x0000fa00 0 0 0 0>;
603 u-boot,dm-pre-reloc;
604 intel,sata-mode = "ahci";
605 intel,sata-port-map = <1>;
606 intel,sata-port0-gen3-tx = <0x72>;
607 reset-gpio = <&gpio_b 15 GPIO_ACTIVE_LOW>;
608 };
609
610 smbus: smbus@1f,3 {
611 compatible = "intel,ich-i2c";
612 reg = <0x0000fb00 0 0 0 0>;
613 u-boot,dm-pre-reloc;
614 };
615 };
616
617 tpm {
618 reg = <0xfed40000 0x5000>;
619 compatible = "infineon,slb9635lpc";
620 };
621
622 microcode {
623 update@0 {
624#include "microcode/mc0306d4_00000018.dtsi"
625 };
626 };
627
628};