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Adam Ford42efb612017-08-07 17:37:18 -04001
2menuconfig NAND
3 bool "NAND Device Support"
4if NAND
Masahiro Yamadac343b382014-10-03 19:21:03 +09005
Masahiro Yamadada0763d2014-11-13 20:31:50 +09006config SYS_NAND_SELF_INIT
7 bool
8 help
9 This option, if enabled, provides more flexible and linux-like
10 NAND initialization process.
11
Masahiro Yamadac343b382014-10-03 19:21:03 +090012config NAND_DENALI
Masahiro Yamadad81d60b2017-12-06 13:51:50 +090013 bool
Masahiro Yamadada0763d2014-11-13 20:31:50 +090014 select SYS_NAND_SELF_INIT
Tom Rini00448d22017-07-28 21:31:42 -040015 imply CMD_NAND
Masahiro Yamadac343b382014-10-03 19:21:03 +090016
Masahiro Yamada9c5a5dd2017-08-26 01:12:31 +090017config NAND_DENALI_DT
18 bool "Support Denali NAND controller as a DT device"
Masahiro Yamadad81d60b2017-12-06 13:51:50 +090019 select NAND_DENALI
20 depends on OF_CONTROL && DM
Masahiro Yamada9c5a5dd2017-08-26 01:12:31 +090021 help
22 Enable the driver for NAND flash on platforms using a Denali NAND
23 controller as a DT device.
24
Masahiro Yamadac343b382014-10-03 19:21:03 +090025config NAND_DENALI_SPARE_AREA_SKIP_BYTES
26 int "Number of bytes skipped in OOB area"
27 depends on NAND_DENALI
28 range 0 63
29 help
30 This option specifies the number of bytes to skip from the beginning
31 of OOB area before last ECC sector data starts. This is potentially
32 used to preserve the bad block marker in the OOB area.
33
Adam Ford5b7c9f02017-10-16 14:08:26 -050034config NAND_OMAP_GPMC
35 bool "Support OMAP GPMC NAND controller"
36 depends on ARCH_OMAP2PLUS
37 help
38 Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
39 GPMC controller is used for parallel NAND flash devices, and can
40 do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
41 and BCH16 ECC algorithms.
42
43config NAND_OMAP_GPMC_PREFETCH
44 bool "Enable GPMC Prefetch"
45 depends on NAND_OMAP_GPMC
Tom Rini848d2672017-10-20 16:55:51 -040046 default y
Adam Ford5b7c9f02017-10-16 14:08:26 -050047 help
48 On OMAP platforms that use the GPMC controller
49 (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
50 uses the prefetch mode to speed up read operations.
51
52config NAND_OMAP_ELM
53 bool "Enable ELM driver for OMAPxx and AMxx platforms."
54 depends on NAND_OMAP_GPMC && !OMAP34XX
55 help
56 ELM controller is used for ECC error detection (not ECC calculation)
57 of BCH4, BCH8 and BCH16 ECC algorithms.
58 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
59 thus such SoC platforms need to depend on software library for ECC error
60 detection. However ECC calculation on such plaforms would still be
61 done by GPMC controller.
62
Stefan Agner6120f752015-05-08 19:07:11 +020063config NAND_VF610_NFC
Heiko Schocher6f90e582017-06-14 05:49:40 +020064 bool "Support for Freescale NFC for VF610"
Stefan Agner6120f752015-05-08 19:07:11 +020065 select SYS_NAND_SELF_INIT
Tom Rini00448d22017-07-28 21:31:42 -040066 imply CMD_NAND
Stefan Agner6120f752015-05-08 19:07:11 +020067 help
68 Enables support for NAND Flash Controller on some Freescale
Heiko Schocher6f90e582017-06-14 05:49:40 +020069 processors like the VF610, MCF54418 or Kinetis K70.
Stefan Agner6120f752015-05-08 19:07:11 +020070 The driver supports a maximum 2k page size. The driver
71 currently does not support hardware ECC.
72
Stefan Agnerfe10d3f2015-05-08 19:07:12 +020073choice
74 prompt "Hardware ECC strength"
75 depends on NAND_VF610_NFC
76 default SYS_NAND_VF610_NFC_45_ECC_BYTES
77 help
78 Select the ECC strength used in the hardware BCH ECC block.
79
80config SYS_NAND_VF610_NFC_45_ECC_BYTES
81 bool "24-error correction (45 ECC bytes)"
82
83config SYS_NAND_VF610_NFC_60_ECC_BYTES
84 bool "32-error correction (60 ECC bytes)"
85
86endchoice
87
Stefan Roese75659da2015-07-23 10:26:16 +020088config NAND_PXA3XX
89 bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
90 select SYS_NAND_SELF_INIT
Tom Rini00448d22017-07-28 21:31:42 -040091 imply CMD_NAND
Stefan Roese75659da2015-07-23 10:26:16 +020092 help
93 This enables the driver for the NAND flash device found on
94 PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
95
Hans de Goede3ce35f92015-08-16 14:48:22 +020096config NAND_SUNXI
Boris Brezillon57f20382016-06-15 21:09:23 +020097 bool "Support for NAND on Allwinner SoCs"
Miquel Raynal38b8a982018-02-28 20:52:00 +010098 default ARCH_SUNXI
Miquel Raynal78f10992018-02-28 20:51:57 +010099 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
Hans de Goede3ce35f92015-08-16 14:48:22 +0200100 select SYS_NAND_SELF_INIT
Maxime Ripard2d3100c2017-02-27 18:22:08 +0100101 select SYS_NAND_U_BOOT_LOCATIONS
Miquel Raynal9f23e002018-02-28 20:51:59 +0100102 select SPL_NAND_SUPPORT
Tom Rini00448d22017-07-28 21:31:42 -0400103 imply CMD_NAND
Hans de Goede3ce35f92015-08-16 14:48:22 +0200104 ---help---
Boris Brezillon57f20382016-06-15 21:09:23 +0200105 Enable support for NAND. This option enables the standard and
106 SPL drivers.
107 The SPL driver only supports reading from the NAND using DMA
108 transfers.
Hans de Goede3ce35f92015-08-16 14:48:22 +0200109
Maxime Ripardfcacc702017-02-27 18:22:12 +0100110if NAND_SUNXI
111
112config NAND_SUNXI_SPL_ECC_STRENGTH
113 int "Allwinner NAND SPL ECC Strength"
114 default 64
115
116config NAND_SUNXI_SPL_ECC_SIZE
117 int "Allwinner NAND SPL ECC Step Size"
118 default 1024
119
120config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
121 int "Allwinner NAND SPL Usable Page Size"
122 default 1024
123
124endif
125
Siva Durga Prasad Paladugu937ad762015-11-17 14:30:09 +0530126config NAND_ARASAN
127 bool "Configure Arasan Nand"
Ezequiel Garcia18a702e2018-01-15 12:48:12 -0300128 select SYS_NAND_SELF_INIT
Tom Rini00448d22017-07-28 21:31:42 -0400129 imply CMD_NAND
Siva Durga Prasad Paladugu937ad762015-11-17 14:30:09 +0530130 help
131 This enables Nand driver support for Arasan nand flash
132 controller. This uses the hardware ECC for read and
133 write operations.
134
Adam Ford5b7c9f02017-10-16 14:08:26 -0500135config NAND_MXC
136 bool "MXC NAND support"
137 depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
138 imply CMD_NAND
139 help
140 This enables the NAND driver for the NAND flash controller on the
141 i.MX27 / i.MX31 / i.MX5 rocessors.
142
Jagan Teki811a8222016-10-08 18:00:25 +0530143config NAND_MXS
144 bool "MXS NAND support"
Stefan Agner3b209fc2018-02-06 09:44:37 +0100145 depends on MX23 || MX28 || MX6 || MX7
Stefan Agner5883e552018-06-22 17:19:47 +0200146 select SYS_NAND_SELF_INIT
Tom Rini00448d22017-07-28 21:31:42 -0400147 imply CMD_NAND
Adam Forda456d562018-02-06 08:34:45 -0600148 select APBH_DMA
149 select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
150 select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
Jagan Teki811a8222016-10-08 18:00:25 +0530151 help
152 This enables NAND driver for the NAND flash controller on the
153 MXS processors.
154
Stefan Agner4d42ac12018-06-22 17:19:51 +0200155if NAND_MXS
156
Stefan Agner150ddbc2018-06-22 18:06:17 +0200157config NAND_MXS_DT
158 bool "Support MXS NAND controller as a DT device"
159 depends on OF_CONTROL && MTD
160 help
161 Enable the driver for MXS NAND flash on platforms using
162 device tree.
163
Stefan Agner4d42ac12018-06-22 17:19:51 +0200164config NAND_MXS_USE_MINIMUM_ECC
165 bool "Use minimum ECC strength supported by the controller"
166 default false
167
168endif
169
Siva Durga Prasad Paladuguc41d5cd2016-09-27 10:55:46 +0530170config NAND_ZYNQ
171 bool "Support for Zynq Nand controller"
172 select SYS_NAND_SELF_INIT
Tom Rini00448d22017-07-28 21:31:42 -0400173 imply CMD_NAND
Siva Durga Prasad Paladuguc41d5cd2016-09-27 10:55:46 +0530174 help
175 This enables Nand driver support for Nand flash controller
176 found on Zynq SoC.
177
Jeff Westfahl313b9c32017-11-06 00:34:46 -0800178config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
179 bool "Enable use of 1st stage bootloader timing for NAND"
180 depends on NAND_ZYNQ
181 help
182 This flag prevent U-boot reconfigure NAND flash controller and reuse
183 the NAND timing from 1st stage bootloader.
184
Stefan Agner6120f752015-05-08 19:07:11 +0200185comment "Generic NAND options"
186
Miquel Raynal639aa982018-02-28 20:52:01 +0100187config SYS_NAND_BLOCK_SIZE
188 hex "NAND chip eraseblock size"
189 depends on ARCH_SUNXI
190 help
191 Number of data bytes in one eraseblock for the NAND chip on the
192 board. This is the multiple of NAND_PAGE_SIZE and the number of
193 pages.
194
195config SYS_NAND_PAGE_SIZE
196 hex "NAND chip page size"
197 depends on ARCH_SUNXI
198 help
199 Number of data bytes in one page for the NAND chip on the
200 board, not including the OOB area.
201
202config SYS_NAND_OOBSIZE
203 hex "NAND chip OOB size"
204 depends on ARCH_SUNXI
205 help
206 Number of bytes in the Out-Of-Band area for the NAND chip on
207 the board.
208
Stefan Agner6120f752015-05-08 19:07:11 +0200209# Enhance depends when converting drivers to Kconfig which use this config
210# option (mxc_nand, ndfc, omap_gpmc).
211config SYS_NAND_BUSWIDTH_16BIT
212 bool "Use 16-bit NAND interface"
Adam Ford5b7c9f02017-10-16 14:08:26 -0500213 depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
Stefan Agner6120f752015-05-08 19:07:11 +0200214 help
215 Indicates that NAND device has 16-bit wide data-bus. In absence of this
216 config, bus-width of NAND device is assumed to be either 8-bit and later
217 determined by reading ONFI params.
218 Above config is useful when NAND device's bus-width information cannot
219 be determined from on-chip ONFI params, like in following scenarios:
220 - SPL boot does not support reading of ONFI parameters. This is done to
221 keep SPL code foot-print small.
222 - In current U-Boot flow using nand_init(), driver initialization
223 happens in board_nand_init() which is called before any device probe
224 (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
225 not available while configuring controller. So a static CONFIG_NAND_xx
226 is needed to know the device's bus-width in advance.
227
Boris Brezillon05b769d2016-06-06 10:16:57 +0200228if SPL
229
230config SYS_NAND_U_BOOT_LOCATIONS
231 bool "Define U-boot binaries locations in NAND"
232 help
233 Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
234 This option should not be enabled when compiling U-boot for boards
235 defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
236 file.
237
Hans de Goede60b1b292015-08-21 21:49:51 +0200238config SYS_NAND_U_BOOT_OFFS
239 hex "Location in NAND to read U-Boot from"
Maxime Riparda15b6ea2017-02-27 18:22:09 +0100240 default 0x800000 if NAND_SUNXI
Boris Brezillon05b769d2016-06-06 10:16:57 +0200241 depends on SYS_NAND_U_BOOT_LOCATIONS
Hans de Goede60b1b292015-08-21 21:49:51 +0200242 help
243 Set the offset from the start of the nand where u-boot should be
244 loaded from.
245
Boris Brezillon4f238e72016-06-06 10:16:58 +0200246config SYS_NAND_U_BOOT_OFFS_REDUND
247 hex "Location in NAND to read U-Boot from"
248 default SYS_NAND_U_BOOT_OFFS
249 depends on SYS_NAND_U_BOOT_LOCATIONS
250 help
251 Set the offset from the start of the nand where the redundant u-boot
252 should be loaded from.
253
Adam Ford5b7c9f02017-10-16 14:08:26 -0500254config SPL_NAND_AM33XX_BCH
255 bool "Enables SPL-NAND driver which supports ELM based"
256 depends on NAND_OMAP_GPMC && !OMAP34XX
257 default y
258 help
259 Hardware ECC correction. This is useful for platforms which have ELM
260 hardware engine and use NAND boot mode.
261 Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
262 so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
263 SPL-NAND driver with software ECC correction support.
264
Masahiro Yamadad182d542014-10-03 19:21:04 +0900265config SPL_NAND_DENALI
266 bool "Support Denali NAND controller for SPL"
267 help
268 This is a small implementation of the Denali NAND controller
269 for use on SPL.
270
Adam Ford5b7c9f02017-10-16 14:08:26 -0500271config SPL_NAND_SIMPLE
272 bool "Use simple SPL NAND driver"
273 depends on !SPL_NAND_AM33XX_BCH
274 help
275 Support for NAND boot using simple NAND drivers that
276 expose the cmd_ctrl() interface.
Masahiro Yamadad182d542014-10-03 19:21:04 +0900277endif
278
Adam Ford42efb612017-08-07 17:37:18 -0400279endif # if NAND