Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 Atmel Corporation. |
| 4 | * Josh Wu <josh.wu@atmel.com> |
| 5 | * |
| 6 | * Configuation settings for the AT91SAM9N12-EK boards. |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __AT91SAM9N12_CONFIG_H_ |
| 10 | #define __AT91SAM9N12_CONFIG_H_ |
| 11 | |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 12 | /* ARM asynchronous clock */ |
| 13 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ |
| 14 | #define CONFIG_SYS_AT91_MAIN_CLOCK 16000000 /* main clock xtal */ |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 15 | |
| 16 | /* Misc CPU related */ |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 17 | |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 18 | /* LCD */ |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 19 | #define LCD_BPP LCD_COLOR16 |
| 20 | #define LCD_OUTPUT_BPP 24 |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 21 | |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 22 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 23 | #define CONFIG_SYS_SDRAM_SIZE 0x08000000 |
| 24 | |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 25 | /* DataFlash */ |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 26 | |
| 27 | /* NAND flash */ |
| 28 | #ifdef CONFIG_CMD_NAND |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 29 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 30 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 31 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 32 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
Andreas Bießmann | a4c24d3 | 2013-11-29 12:13:45 +0100 | [diff] [blame] | 33 | #define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PD(4) |
| 34 | #define CONFIG_SYS_NAND_READY_PIN GPIO_PIN_PD(5) |
Tom Rini | 00448d2 | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 35 | #endif |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 36 | |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 37 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 38 | "console=console=ttyS0,115200\0" \ |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 39 | "bootargs_nand=rootfstype=ubifs ubi.mtd=7 root=ubi0:rootfs rw\0"\ |
| 40 | "bootargs_mmc=root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait\0" |
| 41 | |
Bo Shen | 9c70939 | 2015-03-27 14:23:36 +0800 | [diff] [blame] | 42 | /* SPL */ |
Bo Shen | 9c70939 | 2015-03-27 14:23:36 +0800 | [diff] [blame] | 43 | |
Bo Shen | 9c70939 | 2015-03-27 14:23:36 +0800 | [diff] [blame] | 44 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 45 | |
| 46 | #define CONFIG_SYS_MASTER_CLOCK 132096000 |
| 47 | #define CONFIG_SYS_AT91_PLLA 0x20953f03 |
| 48 | #define CONFIG_SYS_MCKR 0x1301 |
| 49 | #define CONFIG_SYS_MCKR_CSS 0x1302 |
| 50 | |
Wu, Josh | 3f338c1 | 2013-04-16 23:42:44 +0000 | [diff] [blame] | 51 | #endif |