| Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 1 | /* |
| Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 2 | * Copyright (C) 2012-2017 Altera Corporation <www.altera.com> |
| Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 3 | * All rights reserved. |
| 4 | * |
| 5 | * SPDX-License-Identifier: BSD-3-Clause |
| 6 | */ |
| 7 | |
| 8 | #ifndef _FPGA_MANAGER_H_ |
| 9 | #define _FPGA_MANAGER_H_ |
| 10 | |
| 11 | #include <altera.h> |
| 12 | |
| Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 13 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
| 14 | #include <asm/arch/fpga_manager_gen5.h> |
| Tien Fong Chee | 1d675f3 | 2017-07-26 13:05:43 +0800 | [diff] [blame] | 15 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
| 16 | #include <asm/arch/fpga_manager_arria10.h> |
| Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 17 | #endif |
| Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 18 | |
| 19 | /* FPGA CD Ratio Value */ |
| 20 | #define CDRATIO_x1 0x0 |
| 21 | #define CDRATIO_x2 0x1 |
| 22 | #define CDRATIO_x4 0x2 |
| 23 | #define CDRATIO_x8 0x3 |
| 24 | |
| Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 25 | #ifndef __ASSEMBLY__ |
| 26 | |
| 27 | /* Common prototypes */ |
| Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 28 | int fpgamgr_get_mode(void); |
| Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 29 | int fpgamgr_poll_fpga_ready(void); |
| 30 | void fpgamgr_program_write(const void *rbf_data, size_t rbf_size); |
| 31 | int fpgamgr_test_fpga_ready(void); |
| 32 | int fpgamgr_dclkcnt_set(unsigned long cnt); |
| Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 33 | |
| Tien Fong Chee | 31e50f4 | 2017-07-26 13:05:38 +0800 | [diff] [blame] | 34 | #endif /* __ASSEMBLY__ */ |
| Pavel Machek | c721380 | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 35 | #endif /* _FPGA_MANAGER_H_ */ |