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git01.mediatek.com / filogic / uboot / 14ac1241e0f5b9c8095d3acb475cba36a77a3f0c / . / arch / arm / dts / zynqmp-e-a2197-00-revA.dts
blob: 39b5d7fff9ac78a660d4300e28032683d09232df [file] [log] [blame]
Michal Simek4b2ca952019-10-15 12:37:20 +0200[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * dts file for Xilinx Versal a2197 RevA System Controller
4 *
5 * (C) Copyright 2019, Xilinx, Inc.
6 *
7 * Michal Simek <michal.simek@xilinx.com>
8 */
9/dts-v1/;
10
11#include "zynqmp.dtsi"
12#include "zynqmp-clk-ccf.dtsi"
13#include <dt-bindings/gpio/gpio.h>
14#include <dt-bindings/phy/phy.h>
15
16/ {
17 model = "Versal System Controller on a2197 Eval board RevA"; /* VCK190/VMK180 */
18 compatible = "xlnx,zynqmp-e-a2197-00-revA", "xlnx,zynqmp-a2197-revA",
19 "xlnx,zynqmp-a2197", "xlnx,zynqmp";
20
21 aliases {
22 ethernet0 = &gem0;
23 gpio0 = &gpio;
24 i2c0 = &i2c0;
25 i2c1 = &i2c1;
26 mmc0 = &sdhci1;
27 rtc0 = &rtc;
28 serial0 = &uart0;
29 serial1 = &dcc;
30 };
31
32 chosen {
33 bootargs = "earlycon";
34 stdout-path = "serial0:115200n8";
35 xlnx,eeprom = <&eeprom>;
36 };
37
38 memory@0 {
39 device_type = "memory";
40 reg = <0x0 0x0 0x0 0x80000000>;
41 };
42
43 ina226-vccint {
44 compatible = "iio-hwmon";
45 io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
46 };
47 ina226-vcc-soc {
48 compatible = "iio-hwmon";
49 io-channels = <&vcc_soc 0>, <&vcc_soc 1>, <&vcc_soc 2>, <&vcc_soc 3>;
50 };
51 ina226-vcc-pmc {
52 compatible = "iio-hwmon";
53 io-channels = <&vcc_pmc 0>, <&vcc_pmc 1>, <&vcc_pmc 2>, <&vcc_pmc 3>;
54 };
55 ina226-vcc-ram {
56 compatible = "iio-hwmon";
57 io-channels = <&vcc_ram 0>, <&vcc_ram 1>, <&vcc_ram 2>, <&vcc_ram 3>;
58 };
59 ina226-vcc-pslp {
60 compatible = "iio-hwmon";
61 io-channels = <&vcc_pslp 0>, <&vcc_pslp 1>, <&vcc_pslp 2>, <&vcc_pslp 3>;
62 };
63 ina226-vcc-psfp {
64 compatible = "iio-hwmon";
65 io-channels = <&vcc_psfp 0>, <&vcc_psfp 1>, <&vcc_psfp 2>, <&vcc_psfp 3>;
66 };
67 ina226-vccaux {
68 compatible = "iio-hwmon";
69 io-channels = <&vccaux 0>, <&vccaux 1>, <&vccaux 2>, <&vccaux 3>;
70 };
71 ina226-vccaux-pmc {
72 compatible = "iio-hwmon";
73 io-channels = <&vccaux_pmc 0>, <&vccaux_pmc 1>, <&vccaux_pmc 2>, <&vccaux_pmc 3>;
74 };
75 ina226-vcco-500 {
76 compatible = "iio-hwmon";
77 io-channels = <&vcco_500 0>, <&vcco_500 1>, <&vcco_500 2>, <&vcco_500 3>;
78 };
79 ina226-vcco-501 {
80 compatible = "iio-hwmon";
81 io-channels = <&vcco_501 0>, <&vcco_501 1>, <&vcco_501 2>, <&vcco_501 3>;
82 };
83 ina226-vcco-502 {
84 compatible = "iio-hwmon";
85 io-channels = <&vcco_502 0>, <&vcco_502 1>, <&vcco_502 2>, <&vcco_502 3>;
86 };
87 ina226-vcco-503 {
88 compatible = "iio-hwmon";
89 io-channels = <&vcco_503 0>, <&vcco_503 1>, <&vcco_503 2>, <&vcco_503 3>;
90 };
91 ina226-vcc-1v8 {
92 compatible = "iio-hwmon";
93 io-channels = <&vcc_1v8 0>, <&vcc_1v8 1>, <&vcc_1v8 2>, <&vcc_1v8 3>;
94 };
95 ina226-vcc-3v3 {
96 compatible = "iio-hwmon";
97 io-channels = <&vcc_3v3 0>, <&vcc_3v3 1>, <&vcc_3v3 2>, <&vcc_3v3 3>;
98 };
99 ina226-vcc-1v2-ddr4 {
100 compatible = "iio-hwmon";
101 io-channels = <&vcc_1v2_ddr4 0>, <&vcc_1v2_ddr4 1>, <&vcc_1v2_ddr4 2>, <&vcc_1v2_ddr4 3>;
102 };
103 ina226-vcc-1v1-lp4 {
104 compatible = "iio-hwmon";
105 io-channels = <&vcc1v1_lp4 0>, <&vcc1v1_lp4 1>, <&vcc1v1_lp4 2>, <&vcc1v1_lp4 3>;
106 };
107 ina226-vadj-fmc {
108 compatible = "iio-hwmon";
109 io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
110 };
111 ina226-mgtyavcc {
112 compatible = "iio-hwmon";
113 io-channels = <&mgtyavcc 0>, <&mgtyavcc 1>, <&mgtyavcc 2>, <&mgtyavcc 3>;
114 };
115 ina226-mgtyavtt {
116 compatible = "iio-hwmon";
117 io-channels = <&mgtyavtt 0>, <&mgtyavtt 1>, <&mgtyavtt 2>, <&mgtyavtt 3>;
118 };
119 ina226-mgtyvccaux {
120 compatible = "iio-hwmon";
121 io-channels = <&mgtyvccaux 0>, <&mgtyvccaux 1>, <&mgtyvccaux 2>, <&mgtyvccaux 3>;
122 };
123};
124
125&uart0 { /* uart0 MIO38-39 */
126 status = "okay";
127 u-boot,dm-pre-reloc;
128};
129
130&sdhci1 { /* sd1 MIO45-51 cd in place */
131 status = "okay";
132 no-1-8-v;
133 disable-wp;
134 xlnx,mio_bank = <1>;
135};
136
137&gem0 {
138 status = "okay";
139 phy-handle = <&phy0>;
140 phy-mode = "sgmii";
141 is-internal-pcspma;
142 phy0: ethernet-phy@0 { /* u131 M88E1512 */
143 reg = <0>;
144 };
145};
146
147&gpio {
148 status = "okay";
149 gpio-line-names = "", "", "", "", "", /* 0 - 4 */
150 "", "", "DC_SYS_CTRL0", "DC_SYS_CTRL1", "DC_SYS_CTRL2", /* 5 - 9 */
151 "DC_SYS_CTRL3", "ZU4_TRIGGER", "SYSCTLR_PB", "", "", /* 10 - 14 */
152 "", "", "", "", "", /* 15 - 19 */
153 "", "", "", "", "", /* 20 - 24 */
154 "", "", "", "", "", /* 25 - 29 */
155 "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
156 "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
157 "", "", "ETH_RESET_B", "", "", /* 40 - 44 */
158 "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
159 "SD1_CMD", "SD1_CLK", "", "", "", /* 50 - 54 */
160 "", "", "", "", "", /* 55 - 59 */
161 "", "", "", "", "", /* 60 - 64 */
162 "", "", "", "", "", /* 65 - 69 */
163 "", "", "", "", "", /* 70 - 74 */
164 "", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
165 "", "", /* 78 - 79 */
166 "", "", "", "", "", /* 80 - 84 */
167 "", "", "", "", "", /* 85 -89 */
168 "", "", "", "", "", /* 90 - 94 */
169 "", "", "", "", "", /* 95 - 99 */
170 "", "", "", "", "", /* 100 - 104 */
171 "", "", "", "", "", /* 105 - 109 */
172 "", "", "", "", "", /* 110 - 114 */
173 "", "", "", "", "", /* 115 - 119 */
174 "", "", "", "", "", /* 120 - 124 */
175 "", "", "", "", "", /* 125 - 129 */
176 "", "", "", "", "", /* 130 - 134 */
177 "", "", "", "", "", /* 135 - 139 */
178 "", "", "", "", "", /* 140 - 144 */
179 "", "", "", "", "", /* 145 - 149 */
180 "", "", "", "", "", /* 150 - 154 */
181 "", "", "", "", "", /* 155 - 159 */
182 "", "", "", "", "", /* 160 - 164 */
183 "", "", "", "", "", /* 165 - 169 */
184 "", "", "", ""; /* 170 - 174 */
185};
186
187&i2c0 { /* MIO 34-35 - can't stay here */
188 status = "okay";
189 clock-frequency = <400000>;
190 i2c-mux@74 { /* u33 */
191 compatible = "nxp,pca9548";
192 #address-cells = <1>;
193 #size-cells = <0>;
194 reg = <0x74>;
195 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
196 i2c@0 { /* PMBUS */
197 #address-cells = <1>;
198 #size-cells = <0>;
199 reg = <0>;
200 /* u152 IR35215 0x16/0x46 vcc_soc */
201 /* u160 IRPS5401 0x17/0x47 */
202 /* u167 IRPS5401 0x1c/0x4c */
203 /* u175 IRPS5401 0x1d/0x4d */
204 /* u179 ir38164 0x19/0x49 vcco_500 */
205 /* u181 ir38164 0x1a/0x4a vcco_501 */
206 /* u183 ir38164 0x1b/0x4b vcco_502 */
207 /* u185 ir38164 0x1e/0x4e vadj_fmc */
208 /* u187 ir38164 0x1F/0x4f mgtyavcc */
209 /* u189 ir38164 0x20/0x50 mgtyavtt */
210 /* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
211 /* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
212 };
213 i2c@1 { /* PMBUS1_INA226 */
214 #address-cells = <1>;
215 #size-cells = <0>;
216 reg = <1>;
217 /* FIXME check alerts coming to SC */
218 vccint: ina226@40 { /* u65 */
219 compatible = "ti,ina226";
220 #io-channel-cells = <1>;
221 label = "ina226-vccint";
222 reg = <0x40>;
223 shunt-resistor = <5000>; /* R440 */
224 /* 0.78V @ 32A 1 of 6 Phases*/
225 };
226 vcc_soc: ina226@41 { /* u161 */
227 compatible = "ti,ina226";
228 #io-channel-cells = <1>;
229 label = "ina226-vcc-soc";
230 reg = <0x41>;
231 shunt-resistor = <2000>; /* R1186 */
232 /* 0.78V @ 18A */
233 };
234 vcc_pmc: ina226@42 { /* u163 */
235 compatible = "ti,ina226";
236 #io-channel-cells = <1>;
237 label = "ina226-vcc-pmc";
238 reg = <0x42>;
239 shunt-resistor = <5000>; /* R1214 */
240 /* 0.78V @ 500mA */
241 };
242 vcc_ram: ina226@43 { /* u162 */
243 compatible = "ti,ina226";
244 #io-channel-cells = <1>;
245 label = "ina226-vcc-ram";
246 reg = <0x43>;
247 shunt-resistor = <5000>; /* r1221 */
248 /* 0.78V @ 4A */
249 };
250 vcc_pslp: ina226@44 { /* u165 */
251 compatible = "ti,ina226";
252 #io-channel-cells = <1>;
253 label = "ina226-vcc-pslp";
254 reg = <0x44>;
255 shunt-resistor = <5000>; /* R1216 */
256 /* 0.78V @ 1A */
257 };
258 vcc_psfp: ina226@45 { /* u164 */
259 compatible = "ti,ina226";
260 #io-channel-cells = <1>;
261 label = "ina226-vcc-psfp";
262 reg = <0x45>;
263 shunt-resistor = <5000>; /* R1219 */
264 /* 0.78V @ 2A */
265 };
266 };
267 i2c@2 { /* PCIE_CLK */
268 #address-cells = <1>;
269 #size-cells = <0>;
270 reg = <2>;
271 clock_8t49n287: clock-generator@d8 { /* u39 8T49N240 */
272 #clock-cells = <1>; /* author David Cater <david.cater@idt.com>*/
273 compatible = "idt,8t49n240", "idt,8t49n241"; /* FIXME no driver for 240 */
274 reg = <0xd8>;
275 /* Documentation/devicetree/bindings/clock/idt,idt8t49n24x.txt */
276 /* FIXME there input via J241 Samtec CLK1 and CLK0 from U38 - selection PIN */
277 };
278 };
279 i2c@3 { /* PMBUS2_INA226 */
280 #address-cells = <1>;
281 #size-cells = <0>;
282 reg = <3>;
283 /* FIXME check alerts coming to SC */
284 vccaux: ina226@40 { /* u166 */
285 compatible = "ti,ina226";
286 #io-channel-cells = <1>;
287 label = "ina226-vccaux";
288 reg = <0x40>;
289 shunt-resistor = <5000>; /* R382 */
290 /* 1.5V @ 3A */
291 };
292 vccaux_pmc: ina226@41 { /* u168 */
293 compatible = "ti,ina226";
294 #io-channel-cells = <1>;
295 label = "ina226-vccaux-pmc";
296 reg = <0x41>;
297 shunt-resistor = <5000>; /* R1246 */
298 /* 1.5V @ 500mA */
299 };
300 vcco_500: ina226@42 { /* u178 */
301 compatible = "ti,ina226";
302 #io-channel-cells = <1>;
303 label = "ina226-vcco-500";
304 reg = <0x42>;
305 shunt-resistor = <2000>; /* R1300 */
306 /* 3.3V @ 5A */
307 };
308 vcco_501: ina226@43 { /* u180 */
309 compatible = "ti,ina226";
310 #io-channel-cells = <1>;
311 label = "ina226-vcco-501";
312 reg = <0x43>;
313 shunt-resistor = <2000>; /* R1313 */
314 /* 3.3V @ 5A */
315 };
316 vcco_502: ina226@44 { /* u182 */
317 compatible = "ti,ina226";
318 #io-channel-cells = <1>;
319 label = "ina226-vcco-502";
320 reg = <0x44>;
321 shunt-resistor = <2000>; /* R1330 */
322 /* 3.3V @ 5A */
323 };
324 vcco_503: ina226@45 { /* u172 */
325 compatible = "ti,ina226";
326 #io-channel-cells = <1>;
327 label = "ina226-vcco-503";
328 reg = <0x45>;
329 shunt-resistor = <5000>; /* R1229 */
330 /* 1.8V @ 2A */
331 };
332 vcc_1v8: ina226@46 { /* u173 */
333 compatible = "ti,ina226";
334 #io-channel-cells = <1>;
335 label = "ina226-vcc-1v8";
336 reg = <0x46>;
337 shunt-resistor = <5000>; /* R400 */
338 /* 1.8V @ 6A */
339 };
340 vcc_3v3: ina226@47 { /* u174 */
341 compatible = "ti,ina226";
342 #io-channel-cells = <1>;
343 label = "ina226-vcc-3v3";
344 reg = <0x47>;
345 shunt-resistor = <5000>; /* R1232 */
346 /* 3.3V @ 500mA */
347 };
348 vcc_1v2_ddr4: ina226@48 { /* u176 */
349 compatible = "ti,ina226";
350 #io-channel-cells = <1>;
351 label = "ina226-vcc-1v2-ddr4";
352 reg = <0x48>;
353 shunt-resistor = <5000>; /* R1275 */
354 /* 1.2V @ 4A */
355 };
356 vcc1v1_lp4: ina226@49 { /* u177 */
357 compatible = "ti,ina226";
358 #io-channel-cells = <1>;
359 label = "ina226-vcc1v1-lp4";
360 reg = <0x49>;
361 shunt-resistor = <5000>; /* R1286 */
362 /* 1.1V @ 4A */
363 };
364 vadj_fmc: ina226@4a { /* u184 */
365 compatible = "ti,ina226";
366 #io-channel-cells = <1>;
367 label = "ina226-vadj-fmc";
368 reg = <0x4a>;
369 shunt-resistor = <2000>; /* R1350 */
370 /* 1.5V @ 10A */
371 };
372 mgtyavcc: ina226@4b { /* u186 */
373 compatible = "ti,ina226";
374 #io-channel-cells = <1>;
375 label = "ina226-mgtyavcc";
376 reg = <0x4b>;
377 shunt-resistor = <2000>; /* R1367 */
378 /* 0.88V @ 6A */
379 };
380 mgtyavtt: ina226@4c { /* u188 */
381 compatible = "ti,ina226";
382 #io-channel-cells = <1>;
383 label = "ina226-mgtyavtt";
384 reg = <0x4c>;
385 shunt-resistor = <2000>; /* R1384 */
386 /* 1.2V @ 10A */
387 };
388 mgtyvccaux: ina226@4d { /* u234 */
389 compatible = "ti,ina226";
390 #io-channel-cells = <1>;
391 label = "ina226-mgtyvccaux";
392 reg = <0x4d>;
393 shunt-resistor = <5000>; /* r1679 */
394 /* 1.5V @ 500mA */
395 };
396 };
397 i2c@4 { /* LP_I2C_SM */
398 #address-cells = <1>;
399 #size-cells = <0>;
400 reg = <4>;
401 /* FIXME wires ready but chip is missing */
402 };
403 i2c@5 { /* zSFP_SI570 */
404 #address-cells = <1>;
405 #size-cells = <0>;
406 reg = <5>;
407 si570_zsfp: clock-generator@5d { /* u192 */
408 #clock-cells = <0>;
409 compatible = "silabs,si570";
410 reg = <0x5d>;
411 temperature-stability = <50>;
412 factory-fout = <156250000>;
413 clock-frequency = <156250000>;
414 clock-output-names = "si570_hsdp_clk";
415 };
416 };
417 i2c@6 { /* USER_SI570_1 */
418 #address-cells = <1>;
419 #size-cells = <0>;
420 reg = <6>;
421 si570_user1_clk: clock-generator@5d { /* u205 */
422 #clock-cells = <0>;
423 compatible = "silabs,si570";
424 reg = <0x5f>;
425 temperature-stability = <50>;
426 factory-fout = <100000000>;
427 clock-frequency = <100000000>;
428 clock-output-names = "si570_user1";
429 };
430
431 };
432 i2c@7 { /* USER_SI570_2 */
433 #address-cells = <1>;
434 #size-cells = <0>;
435 reg = <7>;
436 /* FIXME wires ready but chip is missing */
437 };
438 };
439};
440
441&i2c1 { /* i2c1 MIO 36-37 */
442 status = "okay";
443 clock-frequency = <400000>;
444
445 i2c-mux@74 { /* u35 */
446 compatible = "nxp,pca9548";
447 #address-cells = <1>;
448 #size-cells = <0>;
449 reg = <0x74>;
450 /* reset-gpios = <&gpio SYSCTLR_IIC_MUX1_RESET_B GPIO_ACTIVE_HIGH>; */
451 dc_i2c: i2c@0 { /* DC_I2C */
452 #address-cells = <1>;
453 #size-cells = <0>;
454 reg = <0>;
455 /* Use for storing information about SC board */
456 eeprom: eeprom@54 { /* u34 - m24128 16kB */
457 compatible = "st,24c128", "atmel,24c128";
458 reg = <0x54>; /* 0x5c too */
459 };
460 si570_ref_clk: clock-generator@5d { /* u32 */
461 #clock-cells = <0>;
462 compatible = "silabs,si570";
463 reg = <0x5d>;
464 temperature-stability = <50>;
465 factory-fout = <33333333>;
466 clock-frequency = <33333333>;
467 clock-output-names = "ref_clk";
468 };
469 /* and connector J212D */
470 };
471 fmc1: i2c@1 { /* FMCP1_IIC */
472 #address-cells = <1>;
473 #size-cells = <0>;
474 reg = <1>;
475 /* FIXME connection to Samtec J51C */
476 /* expected eeprom 0x50 FMC cards */
477 };
478 fmc2: i2c@2 { /* FMCP2_IIC */
479 #address-cells = <1>;
480 #size-cells = <0>;
481 reg = <2>;
482 /* FIXME connection to Samtec J53C */
483 /* expected eeprom 0x50 FMC cards */
484 };
485 i2c@3 { /* DDR4_DIMM1 */
486 #address-cells = <1>;
487 #size-cells = <0>;
488 reg = <3>;
489 si570_ddr_dimm1: clock-generator@60 { /* u2 */
490 #clock-cells = <0>;
491 compatible = "silabs,si570";
492 reg = <0x60>;
493 temperature-stability = <50>;
494 factory-fout = <200000000>;
495 clock-frequency = <200000000>;
496 clock-output-names = "si570_ddrdimm1_clk";
497 };
498 };
499 i2c@4 { /* LPDDR4_SI570_CLK2 */
500 #address-cells = <1>;
501 #size-cells = <0>;
502 reg = <4>;
503 si570_ddr_dimm2: clock-generator@60 { /* u3 */
504 #clock-cells = <0>;
505 compatible = "silabs,si570";
506 reg = <0x60>;
507 temperature-stability = <50>;
508 factory-fout = <200000000>;
509 clock-frequency = <200000000>;
510 clock-output-names = "si570_lpddr4_clk2";
511 };
512 };
513 i2c@5 { /* LPDDR4_SI570_CLK1 */
514 #address-cells = <1>;
515 #size-cells = <0>;
516 reg = <5>;
517 si570_lpddr4: clock-generator@60 { /* u4 */
518 #clock-cells = <0>;
519 compatible = "silabs,si570";
520 reg = <0x60>;
521 temperature-stability = <50>;
522 factory-fout = <200000000>;
523 clock-frequency = <200000000>;
524 clock-output-names = "si570_lpddr4_clk1";
525 };
526 };
527 i2c@6 { /* HSDP_SI570 */
528 #address-cells = <1>;
529 #size-cells = <0>;
530 reg = <6>;
531 si570_hsdp: clock-generator@5d { /* u5 */
532 #clock-cells = <0>;
533 compatible = "silabs,si570";
534 reg = <0x5d>;
535 temperature-stability = <50>;
536 factory-fout = <156250000>;
537 clock-frequency = <156250000>;
538 clock-output-names = "si570_hsdp_clk";
539 };
540 };
541 i2c@7 { /* 8A34001 - U219B and J310 connector */
542 #address-cells = <1>;
543 #size-cells = <0>;
544 reg = <7>;
545 };
546 };
547};
548
549&xilinx_ams {
550 status = "okay";
551};
552
553&ams_ps {
554 status = "okay";
555};
556
557&ams_pl {
558 status = "okay";
559};