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git01.mediatek.com / filogic / uboot / 14ac1241e0f5b9c8095d3acb475cba36a77a3f0c / . / arch / arm / dts / imx8mq-evk.dts
blob: 3693933451473fa54940fce3fcb559d71421511c [file] [log] [blame]
Patrick Wildt02548cf2019-10-14 13:19:00 +0200[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/*
3 * Copyright 2017 NXP
4 * Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
5 */
6
7/dts-v1/;
8
9/* First 128KB is for PSCI ATF. */
10/memreserve/ 0x40000000 0x00020000;
11
12#include "imx8mq.dtsi"
13
14/ {
15 model = "NXP i.MX8MQ EVK";
16 compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
17
18 chosen {
19 stdout-path = &uart1;
20 };
21
22 memory@40000000 {
23 device_type = "memory";
24 reg = <0x00000000 0x40000000 0 0xc0000000>;
25 };
26
27 pcie0_refclk: pcie0-refclk {
28 compatible = "fixed-clock";
29 #clock-cells = <0>;
30 clock-frequency = <100000000>;
31 };
32
33 reg_usdhc2_vmmc: regulator-vsd-3v3 {
34 pinctrl-names = "default";
35 pinctrl-0 = <&pinctrl_reg_usdhc2>;
36 compatible = "regulator-fixed";
37 regulator-name = "VSD_3V3";
38 regulator-min-microvolt = <3300000>;
39 regulator-max-microvolt = <3300000>;
40 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
41 enable-active-high;
42 };
43
44 buck2_reg: regulator-buck2 {
45 pinctrl-names = "default";
46 pinctrl-0 = <&pinctrl_buck2>;
47 compatible = "regulator-gpio";
48 regulator-name = "vdd_arm";
49 regulator-min-microvolt = <900000>;
50 regulator-max-microvolt = <1000000>;
51 gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
52 states = <1000000 0x0
53 900000 0x1>;
54 };
55
56 wm8524: audio-codec {
57 #sound-dai-cells = <0>;
58 compatible = "wlf,wm8524";
59 wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
60 };
61
62 sound-wm8524 {
63 compatible = "simple-audio-card";
64 simple-audio-card,name = "wm8524-audio";
65 simple-audio-card,format = "i2s";
66 simple-audio-card,frame-master = <&cpudai>;
67 simple-audio-card,bitclock-master = <&cpudai>;
68 simple-audio-card,widgets =
69 "Line", "Left Line Out Jack",
70 "Line", "Right Line Out Jack";
71 simple-audio-card,routing =
72 "Left Line Out Jack", "LINEVOUTL",
73 "Right Line Out Jack", "LINEVOUTR";
74
75 cpudai: simple-audio-card,cpu {
76 sound-dai = <&sai2>;
77 };
78
79 link_codec: simple-audio-card,codec {
80 sound-dai = <&wm8524>;
81 clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>;
82 };
83 };
84};
85
86&A53_0 {
87 cpu-supply = <&buck2_reg>;
88};
89
90&A53_1 {
91 cpu-supply = <&buck2_reg>;
92};
93
94&A53_2 {
95 cpu-supply = <&buck2_reg>;
96};
97
98&A53_3 {
99 cpu-supply = <&buck2_reg>;
100};
101
102&fec1 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_fec1>;
105 phy-mode = "rgmii-id";
106 phy-handle = <&ethphy0>;
107 fsl,magic-packet;
108 status = "okay";
109
110 mdio {
111 #address-cells = <1>;
112 #size-cells = <0>;
113
114 ethphy0: ethernet-phy@0 {
115 compatible = "ethernet-phy-ieee802.3-c22";
116 reg = <0>;
117 };
118 };
119};
120
121&sai2 {
122 pinctrl-names = "default";
123 pinctrl-0 = <&pinctrl_sai2>;
124 assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1_BYPASS>, <&clk IMX8MQ_CLK_SAI2>;
125 assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL1_OUT>;
126 assigned-clock-rates = <0>, <24576000>;
127 status = "okay";
128};
129
130&gpio5 {
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_wifi_reset>;
133
134 wl-reg-on {
135 gpio-hog;
136 gpios = <29 GPIO_ACTIVE_HIGH>;
137 output-high;
138 };
139};
140
141&i2c1 {
142 clock-frequency = <100000>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_i2c1>;
145 status = "okay";
146
147 pmic@8 {
148 compatible = "fsl,pfuze100";
149 reg = <0x8>;
150
151 regulators {
152 sw1a_reg: sw1ab {
153 regulator-min-microvolt = <825000>;
154 regulator-max-microvolt = <1100000>;
155 };
156
157 sw1c_reg: sw1c {
158 regulator-min-microvolt = <825000>;
159 regulator-max-microvolt = <1100000>;
160 };
161
162 sw2_reg: sw2 {
163 regulator-min-microvolt = <1100000>;
164 regulator-max-microvolt = <1100000>;
165 regulator-always-on;
166 };
167
168 sw3a_reg: sw3ab {
169 regulator-min-microvolt = <825000>;
170 regulator-max-microvolt = <1100000>;
171 regulator-always-on;
172 };
173
174 sw4_reg: sw4 {
175 regulator-min-microvolt = <1800000>;
176 regulator-max-microvolt = <1800000>;
177 regulator-always-on;
178 };
179
180 swbst_reg: swbst {
181 regulator-min-microvolt = <5000000>;
182 regulator-max-microvolt = <5150000>;
183 };
184
185 snvs_reg: vsnvs {
186 regulator-min-microvolt = <1000000>;
187 regulator-max-microvolt = <3000000>;
188 regulator-always-on;
189 };
190
191 vref_reg: vrefddr {
192 regulator-always-on;
193 };
194
195 vgen1_reg: vgen1 {
196 regulator-min-microvolt = <800000>;
197 regulator-max-microvolt = <1550000>;
198 };
199
200 vgen2_reg: vgen2 {
201 regulator-min-microvolt = <850000>;
202 regulator-max-microvolt = <975000>;
203 regulator-always-on;
204 };
205
206 vgen3_reg: vgen3 {
207 regulator-min-microvolt = <1675000>;
208 regulator-max-microvolt = <1975000>;
209 regulator-always-on;
210 };
211
212 vgen4_reg: vgen4 {
213 regulator-min-microvolt = <1625000>;
214 regulator-max-microvolt = <1875000>;
215 regulator-always-on;
216 };
217
218 vgen5_reg: vgen5 {
219 regulator-min-microvolt = <3075000>;
220 regulator-max-microvolt = <3625000>;
221 regulator-always-on;
222 };
223
224 vgen6_reg: vgen6 {
225 regulator-min-microvolt = <1800000>;
226 regulator-max-microvolt = <3300000>;
227 };
228 };
229 };
230};
231
232&pcie0 {
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_pcie0>;
235 reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>;
236 clocks = <&clk IMX8MQ_CLK_PCIE1_ROOT>,
237 <&clk IMX8MQ_CLK_PCIE1_AUX>,
238 <&clk IMX8MQ_CLK_PCIE1_PHY>,
239 <&pcie0_refclk>;
240 clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
241 status = "okay";
242};
243
244&pgc_gpu {
245 power-supply = <&sw1a_reg>;
246};
247
248&snvs_pwrkey {
249 status = "okay";
250};
251
252&uart1 {
253 pinctrl-names = "default";
254 pinctrl-0 = <&pinctrl_uart1>;
255 status = "okay";
256};
257
258&usb3_phy1 {
259 status = "okay";
260};
261
262&usb_dwc3_1 {
263 dr_mode = "host";
264 status = "okay";
265};
266
267&qspi0 {
268 pinctrl-names = "default";
269 pinctrl-0 = <&pinctrl_qspi>;
270 status = "okay";
271
272 n25q256a: flash@0 {
273 reg = <0>;
274 #address-cells = <1>;
275 #size-cells = <1>;
276 compatible = "micron,n25q256a", "jedec,spi-nor";
277 spi-max-frequency = <29000000>;
278 };
279};
280
281&usdhc1 {
282 pinctrl-names = "default", "state_100mhz", "state_200mhz";
283 pinctrl-0 = <&pinctrl_usdhc1>;
284 pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
285 pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
286 vqmmc-supply = <&sw4_reg>;
287 bus-width = <8>;
288 non-removable;
289 no-sd;
290 no-sdio;
291 status = "okay";
292};
293
294&usdhc2 {
295 pinctrl-names = "default", "state_100mhz", "state_200mhz";
296 pinctrl-0 = <&pinctrl_usdhc2>;
297 pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
298 pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
299 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
300 vmmc-supply = <&reg_usdhc2_vmmc>;
301 status = "okay";
302};
303
304&wdog1 {
305 pinctrl-names = "default";
306 pinctrl-0 = <&pinctrl_wdog>;
307 fsl,ext-reset-output;
308 status = "okay";
309};
310
311&iomuxc {
312 pinctrl_buck2: vddarmgrp {
313 fsl,pins = <
314 MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x19
315 >;
316
317 };
318
319 pinctrl_fec1: fec1grp {
320 fsl,pins = <
321 MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3
322 MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
323 MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
324 MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
325 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
326 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
327 MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
328 MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
329 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
330 MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
331 MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
332 MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
333 MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
334 MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
335 MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19
336 >;
337 };
338
339 pinctrl_i2c1: i2c1grp {
340 fsl,pins = <
341 MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f
342 MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f
343 >;
344 };
345
346 pinctrl_pcie0: pcie0grp {
347 fsl,pins = <
348 MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76
349 MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16
350 >;
351 };
352
353 pinctrl_qspi: qspigrp {
354 fsl,pins = <
355 MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82
356 MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
357 MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
358 MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
359 MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
360 MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
361
362 >;
363 };
364
365 pinctrl_reg_usdhc2: regusdhc2grpgpio {
366 fsl,pins = <
367 MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
368 >;
369 };
370
371 pinctrl_sai2: sai2grp {
372 fsl,pins = <
373 MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
374 MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
375 MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6
376 MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
377 MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6
378 >;
379 };
380
381 pinctrl_uart1: uart1grp {
382 fsl,pins = <
383 MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49
384 MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49
385 >;
386 };
387
388 pinctrl_usdhc1: usdhc1grp {
389 fsl,pins = <
390 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83
391 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3
392 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3
393 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3
394 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3
395 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3
396 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3
397 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3
398 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3
399 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3
400 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83
401 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
402 >;
403 };
404
405 pinctrl_usdhc1_100mhz: usdhc1-100grp {
406 fsl,pins = <
407 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
408 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
409 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd
410 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd
411 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd
412 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd
413 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd
414 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd
415 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd
416 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd
417 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d
418 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
419 >;
420 };
421
422 pinctrl_usdhc1_200mhz: usdhc1-200grp {
423 fsl,pins = <
424 MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
425 MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
426 MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf
427 MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf
428 MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf
429 MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf
430 MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf
431 MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf
432 MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf
433 MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf
434 MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f
435 MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1
436 >;
437 };
438
439 pinctrl_usdhc2: usdhc2grp {
440 fsl,pins = <
441 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83
442 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3
443 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3
444 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3
445 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3
446 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3
447 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
448 >;
449 };
450
451 pinctrl_usdhc2_100mhz: usdhc2-100grp {
452 fsl,pins = <
453 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
454 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
455 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc5
456 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc5
457 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc5
458 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc5
459 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
460 >;
461 };
462
463 pinctrl_usdhc2_200mhz: usdhc2-200grp {
464 fsl,pins = <
465 MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
466 MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
467 MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc7
468 MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc7
469 MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc7
470 MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc7
471 MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1
472 >;
473 };
474
475 pinctrl_wdog: wdog1grp {
476 fsl,pins = <
477 MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
478 >;
479 };
480
481 pinctrl_wifi_reset: wifiresetgrp {
482 fsl,pins = <
483 MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16
484 >;
485 };
486};