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wdenk78f66222002-08-27 10:27:51 +00001/*
2 * (C) Copyright 2000
3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24#include <common.h>
25
26#ifdef CFG_NS16550_SERIAL
27
28#include <ns16550.h>
29#ifdef CFG_NS87308
30#include <ns87308.h>
31#endif
32
Wolfgang Denk6405a152006-03-31 18:32:53 +020033DECLARE_GLOBAL_DATA_PTR;
34
wdenke0c812a2005-04-03 15:51:42 +000035#if !defined(CONFIG_CONS_INDEX)
36#error "No console index specified."
37#elif (CONFIG_CONS_INDEX < 1) || (CONFIG_CONS_INDEX > 4)
38#error "Invalid console index value."
39#endif
40
41#if CONFIG_CONS_INDEX == 1 && !defined(CFG_NS16550_COM1)
42#error "Console port 1 defined but not configured."
43#elif CONFIG_CONS_INDEX == 2 && !defined(CFG_NS16550_COM2)
44#error "Console port 2 defined but not configured."
45#elif CONFIG_CONS_INDEX == 3 && !defined(CFG_NS16550_COM3)
46#error "Console port 3 defined but not configured."
47#elif CONFIG_CONS_INDEX == 4 && !defined(CFG_NS16550_COM4)
48#error "Console port 4 defined but not configured."
49#endif
50
51/* Note: The port number specified in the functions is 1 based.
52 * the array is 0 based.
53 */
54static NS16550_t serial_ports[4] = {
55#ifdef CFG_NS16550_COM1
56 (NS16550_t)CFG_NS16550_COM1,
wdenk78f66222002-08-27 10:27:51 +000057#else
wdenke0c812a2005-04-03 15:51:42 +000058 NULL,
wdenk78f66222002-08-27 10:27:51 +000059#endif
wdenke0c812a2005-04-03 15:51:42 +000060#ifdef CFG_NS16550_COM2
61 (NS16550_t)CFG_NS16550_COM2,
62#else
63 NULL,
64#endif
65#ifdef CFG_NS16550_COM3
66 (NS16550_t)CFG_NS16550_COM3,
67#else
68 NULL,
69#endif
70#ifdef CFG_NS16550_COM4
71 (NS16550_t)CFG_NS16550_COM4
72#else
73 NULL
74#endif
75};
wdenk78f66222002-08-27 10:27:51 +000076
wdenke0c812a2005-04-03 15:51:42 +000077#define PORT serial_ports[port-1]
78#define CONSOLE (serial_ports[CONFIG_CONS_INDEX-1])
79
80static int calc_divisor (NS16550_t port)
wdenk78f66222002-08-27 10:27:51 +000081{
wdenkf6f96f72003-07-15 20:04:06 +000082#ifdef CONFIG_OMAP1510
83 /* If can't cleanly clock 115200 set div to 1 */
84 if ((CFG_NS16550_CLK == 12000000) && (gd->baudrate == 115200)) {
wdenke0c812a2005-04-03 15:51:42 +000085 port->osc_12m_sel = OSC_12M_SEL; /* enable 6.5 * divisor */
wdenkf6f96f72003-07-15 20:04:06 +000086 return (1); /* return 1 for base divisor */
87 }
wdenke0c812a2005-04-03 15:51:42 +000088 port->osc_12m_sel = 0; /* clear if previsouly set */
wdenkf6f96f72003-07-15 20:04:06 +000089#endif
wdenk7eaacc52003-08-29 22:00:43 +000090#ifdef CONFIG_OMAP1610
91 /* If can't cleanly clock 115200 set div to 1 */
92 if ((CFG_NS16550_CLK == 48000000) && (gd->baudrate == 115200)) {
93 return (26); /* return 26 for base divisor */
94 }
95#endif
wdenkf8062712005-01-09 23:16:25 +000096
97#ifdef CONFIG_APTIX
98#define MODE_X_DIV 13
99#else
100#define MODE_X_DIV 16
101#endif
102 return (CFG_NS16550_CLK / MODE_X_DIV / gd->baudrate);
103
wdenkf6f96f72003-07-15 20:04:06 +0000104}
wdenk78f66222002-08-27 10:27:51 +0000105
wdenkf6f96f72003-07-15 20:04:06 +0000106int serial_init (void)
107{
wdenke0c812a2005-04-03 15:51:42 +0000108 int clock_divisor;
wdenk78f66222002-08-27 10:27:51 +0000109
110#ifdef CFG_NS87308
111 initialise_ns87308();
112#endif
113
wdenke0c812a2005-04-03 15:51:42 +0000114#ifdef CFG_NS16550_COM1
115 clock_divisor = calc_divisor(serial_ports[0]);
116 NS16550_init(serial_ports[0], clock_divisor);
117#endif
118#ifdef CFG_NS16550_COM2
119 clock_divisor = calc_divisor(serial_ports[1]);
120 NS16550_init(serial_ports[1], clock_divisor);
121#endif
122#ifdef CFG_NS16550_COM3
123 clock_divisor = calc_divisor(serial_ports[2]);
124 NS16550_init(serial_ports[2], clock_divisor);
125#endif
126#ifdef CFG_NS16550_COM4
127 clock_divisor = calc_divisor(serial_ports[3]);
128 NS16550_init(serial_ports[3], clock_divisor);
129#endif
wdenk78f66222002-08-27 10:27:51 +0000130
131 return (0);
132}
133
134void
wdenke0c812a2005-04-03 15:51:42 +0000135_serial_putc(const char c,const int port)
wdenk78f66222002-08-27 10:27:51 +0000136{
137 if (c == '\n')
wdenke0c812a2005-04-03 15:51:42 +0000138 NS16550_putc(PORT, '\r');
139
140 NS16550_putc(PORT, c);
141}
wdenk78f66222002-08-27 10:27:51 +0000142
wdenke0c812a2005-04-03 15:51:42 +0000143void
144_serial_putc_raw(const char c,const int port)
145{
146 NS16550_putc(PORT, c);
wdenk78f66222002-08-27 10:27:51 +0000147}
148
149void
wdenke0c812a2005-04-03 15:51:42 +0000150_serial_puts (const char *s,const int port)
wdenk78f66222002-08-27 10:27:51 +0000151{
152 while (*s) {
wdenke0c812a2005-04-03 15:51:42 +0000153 _serial_putc (*s++,port);
wdenk78f66222002-08-27 10:27:51 +0000154 }
155}
156
157
158int
wdenke0c812a2005-04-03 15:51:42 +0000159_serial_getc(const int port)
wdenk78f66222002-08-27 10:27:51 +0000160{
wdenke0c812a2005-04-03 15:51:42 +0000161 return NS16550_getc(PORT);
wdenk78f66222002-08-27 10:27:51 +0000162}
163
164int
wdenke0c812a2005-04-03 15:51:42 +0000165_serial_tstc(const int port)
wdenk78f66222002-08-27 10:27:51 +0000166{
wdenke0c812a2005-04-03 15:51:42 +0000167 return NS16550_tstc(PORT);
wdenk78f66222002-08-27 10:27:51 +0000168}
169
170void
wdenke0c812a2005-04-03 15:51:42 +0000171_serial_setbrg (const int port)
wdenk78f66222002-08-27 10:27:51 +0000172{
wdenkf6f96f72003-07-15 20:04:06 +0000173 int clock_divisor;
wdenk78f66222002-08-27 10:27:51 +0000174
wdenke0c812a2005-04-03 15:51:42 +0000175 clock_divisor = calc_divisor(PORT);
176 NS16550_reinit(PORT, clock_divisor);
177}
178
179void
180serial_putc(const char c)
181{
182 _serial_putc(c,CONFIG_CONS_INDEX);
183}
184
185void
186serial_putc_raw(const char c)
187{
188 _serial_putc_raw(c,CONFIG_CONS_INDEX);
189}
190
191void
192serial_puts(const char *s)
193{
194 _serial_puts(s,CONFIG_CONS_INDEX);
195}
196
197int
198serial_getc(void)
199{
200 return _serial_getc(CONFIG_CONS_INDEX);
201}
202
203int
204serial_tstc(void)
205{
206 return _serial_tstc(CONFIG_CONS_INDEX);
207}
208
209void
210serial_setbrg(void)
211{
212 _serial_setbrg(CONFIG_CONS_INDEX);
wdenk78f66222002-08-27 10:27:51 +0000213}
214
215#endif