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git01.mediatek.com / filogic / uboot / 1470ce22282482cf1547798875fbc8039a143f15 / . / arch / riscv / dts / fu540-c000.dtsi
blob: afa43c7ea3690db3fceb535759652a9488d22049 [file] [log] [blame]
Jagan Tekia8ed6262019-11-18 16:59:40 +0530[diff] [blame]1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2018-2019 SiFive, Inc */
3
4/dts-v1/;
5
6#include <dt-bindings/clock/sifive-fu540-prci.h>
7
8/ {
9 #address-cells = <2>;
10 #size-cells = <2>;
11 compatible = "sifive,fu540-c000", "sifive,fu540";
12
13 aliases {
14 serial0 = &uart0;
15 serial1 = &uart1;
16 ethernet0 = &eth0;
17 };
18
19 chosen {
20 };
21
22 cpus {
23 #address-cells = <1>;
24 #size-cells = <0>;
25 cpu0: cpu@0 {
26 compatible = "sifive,e51", "sifive,rocket0", "riscv";
27 device_type = "cpu";
28 i-cache-block-size = <64>;
29 i-cache-sets = <128>;
30 i-cache-size = <16384>;
31 reg = <0>;
32 riscv,isa = "rv64imac";
33 status = "disabled";
34 cpu0_intc: interrupt-controller {
35 #interrupt-cells = <1>;
36 compatible = "riscv,cpu-intc";
37 interrupt-controller;
38 };
39 };
40 cpu1: cpu@1 {
41 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
42 d-cache-block-size = <64>;
43 d-cache-sets = <64>;
44 d-cache-size = <32768>;
45 d-tlb-sets = <1>;
46 d-tlb-size = <32>;
47 device_type = "cpu";
48 i-cache-block-size = <64>;
49 i-cache-sets = <64>;
50 i-cache-size = <32768>;
51 i-tlb-sets = <1>;
52 i-tlb-size = <32>;
53 mmu-type = "riscv,sv39";
54 reg = <1>;
55 riscv,isa = "rv64imafdc";
56 tlb-split;
57 cpu1_intc: interrupt-controller {
58 #interrupt-cells = <1>;
59 compatible = "riscv,cpu-intc";
60 interrupt-controller;
61 };
62 };
63 cpu2: cpu@2 {
64 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
65 d-cache-block-size = <64>;
66 d-cache-sets = <64>;
67 d-cache-size = <32768>;
68 d-tlb-sets = <1>;
69 d-tlb-size = <32>;
70 device_type = "cpu";
71 i-cache-block-size = <64>;
72 i-cache-sets = <64>;
73 i-cache-size = <32768>;
74 i-tlb-sets = <1>;
75 i-tlb-size = <32>;
76 mmu-type = "riscv,sv39";
77 reg = <2>;
78 riscv,isa = "rv64imafdc";
79 tlb-split;
80 cpu2_intc: interrupt-controller {
81 #interrupt-cells = <1>;
82 compatible = "riscv,cpu-intc";
83 interrupt-controller;
84 };
85 };
86 cpu3: cpu@3 {
87 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
88 d-cache-block-size = <64>;
89 d-cache-sets = <64>;
90 d-cache-size = <32768>;
91 d-tlb-sets = <1>;
92 d-tlb-size = <32>;
93 device_type = "cpu";
94 i-cache-block-size = <64>;
95 i-cache-sets = <64>;
96 i-cache-size = <32768>;
97 i-tlb-sets = <1>;
98 i-tlb-size = <32>;
99 mmu-type = "riscv,sv39";
100 reg = <3>;
101 riscv,isa = "rv64imafdc";
102 tlb-split;
103 cpu3_intc: interrupt-controller {
104 #interrupt-cells = <1>;
105 compatible = "riscv,cpu-intc";
106 interrupt-controller;
107 };
108 };
109 cpu4: cpu@4 {
110 compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
111 d-cache-block-size = <64>;
112 d-cache-sets = <64>;
113 d-cache-size = <32768>;
114 d-tlb-sets = <1>;
115 d-tlb-size = <32>;
116 device_type = "cpu";
117 i-cache-block-size = <64>;
118 i-cache-sets = <64>;
119 i-cache-size = <32768>;
120 i-tlb-sets = <1>;
121 i-tlb-size = <32>;
122 mmu-type = "riscv,sv39";
123 reg = <4>;
124 riscv,isa = "rv64imafdc";
125 tlb-split;
126 cpu4_intc: interrupt-controller {
127 #interrupt-cells = <1>;
128 compatible = "riscv,cpu-intc";
129 interrupt-controller;
130 };
131 };
132 };
133 soc {
134 #address-cells = <2>;
135 #size-cells = <2>;
136 compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
137 ranges;
138 plic0: interrupt-controller@c000000 {
139 #interrupt-cells = <1>;
140 compatible = "sifive,plic-1.0.0";
141 reg = <0x0 0xc000000 0x0 0x4000000>;
142 riscv,ndev = <53>;
143 interrupt-controller;
144 interrupts-extended = <
145 &cpu0_intc 0xffffffff
146 &cpu1_intc 0xffffffff &cpu1_intc 9
147 &cpu2_intc 0xffffffff &cpu2_intc 9
148 &cpu3_intc 0xffffffff &cpu3_intc 9
149 &cpu4_intc 0xffffffff &cpu4_intc 9>;
150 };
151 prci: clock-controller@10000000 {
152 compatible = "sifive,fu540-c000-prci";
153 reg = <0x0 0x10000000 0x0 0x1000>;
154 clocks = <&hfclk>, <&rtcclk>;
155 #clock-cells = <1>;
156 };
157 uart0: serial@10010000 {
158 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
159 reg = <0x0 0x10010000 0x0 0x1000>;
160 interrupt-parent = <&plic0>;
161 interrupts = <4>;
162 clocks = <&prci PRCI_CLK_TLCLK>;
163 status = "disabled";
164 };
165 uart1: serial@10011000 {
166 compatible = "sifive,fu540-c000-uart", "sifive,uart0";
167 reg = <0x0 0x10011000 0x0 0x1000>;
168 interrupt-parent = <&plic0>;
169 interrupts = <5>;
170 clocks = <&prci PRCI_CLK_TLCLK>;
171 status = "disabled";
172 };
173 i2c0: i2c@10030000 {
174 compatible = "sifive,fu540-c000-i2c", "sifive,i2c0";
175 reg = <0x0 0x10030000 0x0 0x1000>;
176 interrupt-parent = <&plic0>;
177 interrupts = <50>;
178 clocks = <&prci PRCI_CLK_TLCLK>;
179 reg-shift = <2>;
180 reg-io-width = <1>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 status = "disabled";
184 };
185 qspi0: spi@10040000 {
186 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
187 reg = <0x0 0x10040000 0x0 0x1000
188 0x0 0x20000000 0x0 0x10000000>;
189 interrupt-parent = <&plic0>;
190 interrupts = <51>;
191 clocks = <&prci PRCI_CLK_TLCLK>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 status = "disabled";
195 };
196 qspi1: spi@10041000 {
197 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
198 reg = <0x0 0x10041000 0x0 0x1000
199 0x0 0x30000000 0x0 0x10000000>;
200 interrupt-parent = <&plic0>;
201 interrupts = <52>;
202 clocks = <&prci PRCI_CLK_TLCLK>;
203 #address-cells = <1>;
204 #size-cells = <0>;
205 status = "disabled";
206 };
207 qspi2: spi@10050000 {
208 compatible = "sifive,fu540-c000-spi", "sifive,spi0";
209 reg = <0x0 0x10050000 0x0 0x1000>;
210 interrupt-parent = <&plic0>;
211 interrupts = <6>;
212 clocks = <&prci PRCI_CLK_TLCLK>;
213 #address-cells = <1>;
214 #size-cells = <0>;
215 status = "disabled";
216 };
217 eth0: ethernet@10090000 {
218 compatible = "sifive,fu540-c000-gem";
219 interrupt-parent = <&plic0>;
220 interrupts = <53>;
221 reg = <0x0 0x10090000 0x0 0x2000
222 0x0 0x100a0000 0x0 0x1000>;
223 local-mac-address = [00 00 00 00 00 00];
224 clock-names = "pclk", "hclk";
225 clocks = <&prci PRCI_CLK_GEMGXLPLL>,
226 <&prci PRCI_CLK_GEMGXLPLL>;
227 #address-cells = <1>;
228 #size-cells = <0>;
229 status = "disabled";
230 };
231 pwm0: pwm@10020000 {
232 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
233 reg = <0x0 0x10020000 0x0 0x1000>;
234 interrupt-parent = <&plic0>;
235 interrupts = <42 43 44 45>;
236 clocks = <&prci PRCI_CLK_TLCLK>;
237 #pwm-cells = <3>;
238 status = "disabled";
239 };
240 pwm1: pwm@10021000 {
241 compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
242 reg = <0x0 0x10021000 0x0 0x1000>;
243 interrupt-parent = <&plic0>;
244 interrupts = <46 47 48 49>;
245 clocks = <&prci PRCI_CLK_TLCLK>;
246 #pwm-cells = <3>;
247 status = "disabled";
248 };
249
250 };
251};