Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 146c3b5e653cf8cc18311d1ba9569f84fc17ad7a / . / arch / arm / mach-imx / mx7 / ddr.c
blob: 9713835bf275a0edfcf2e7bdbf2bc7b91a76ab84 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]2/*
3 * DDR controller configuration for the i.MX7 architecture
4 *
5 * (C) Copyright 2017 CompuLab, Ltd. http://www.compulab.com
6 *
7 * Author: Uri Mashiach <uri.mashiach@compulab.co.il>
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]8 */
9
10#include <linux/types.h>
11#include <asm/io.h>
12#include <asm/arch/imx-regs.h>
13#include <asm/arch/crm_regs.h>
14#include <asm/arch/mx7-ddr.h>
15#include <common.h>
16
17/*
18 * Routine: mx7_dram_cfg
19 * Description: DDR controller configuration
20 *
21 * @ddrc_regs_val: DDRC registers value
22 * @ddrc_mp_val: DDRC_MP registers value
23 * @ddr_phy_regs_val: DDR_PHY registers value
24 * @calib_param: calibration parameters
25 *
26 */
27void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val,
28 struct ddr_phy *ddr_phy_regs_val,
29 struct mx7_calibration *calib_param)
30{
31 struct src *const src_regs = (struct src *)SRC_BASE_ADDR;
32 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
33 struct ddrc_mp *const ddrc_mp_reg = (struct ddrc_mp *)DDRC_MP_BASE_ADDR;
34 struct ddr_phy *const ddr_phy_regs =
35 (struct ddr_phy *)DDRPHY_IPS_BASE_ADDR;
36 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =
37 (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
38 int i;
39
40 /* Assert DDR Controller preset and DDR PHY reset */
41 writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr);
42
43 /* DDR controller configuration */
44 writel(ddrc_regs_val->mstr, &ddrc_regs->mstr);
45 writel(ddrc_regs_val->rfshtmg, &ddrc_regs->rfshtmg);
46 writel(ddrc_mp_val->pctrl_0, &ddrc_mp_reg->pctrl_0);
47 writel(ddrc_regs_val->init1, &ddrc_regs->init1);
48 writel(ddrc_regs_val->init0, &ddrc_regs->init0);
49 writel(ddrc_regs_val->init3, &ddrc_regs->init3);
50 writel(ddrc_regs_val->init4, &ddrc_regs->init4);
51 writel(ddrc_regs_val->init5, &ddrc_regs->init5);
52 writel(ddrc_regs_val->rankctl, &ddrc_regs->rankctl);
53 writel(ddrc_regs_val->dramtmg0, &ddrc_regs->dramtmg0);
54 writel(ddrc_regs_val->dramtmg1, &ddrc_regs->dramtmg1);
55 writel(ddrc_regs_val->dramtmg2, &ddrc_regs->dramtmg2);
56 writel(ddrc_regs_val->dramtmg3, &ddrc_regs->dramtmg3);
57 writel(ddrc_regs_val->dramtmg4, &ddrc_regs->dramtmg4);
58 writel(ddrc_regs_val->dramtmg5, &ddrc_regs->dramtmg5);
59 writel(ddrc_regs_val->dramtmg8, &ddrc_regs->dramtmg8);
60 writel(ddrc_regs_val->zqctl0, &ddrc_regs->zqctl0);
61 writel(ddrc_regs_val->dfitmg0, &ddrc_regs->dfitmg0);
62 writel(ddrc_regs_val->dfitmg1, &ddrc_regs->dfitmg1);
63 writel(ddrc_regs_val->dfiupd0, &ddrc_regs->dfiupd0);
64 writel(ddrc_regs_val->dfiupd1, &ddrc_regs->dfiupd1);
65 writel(ddrc_regs_val->dfiupd2, &ddrc_regs->dfiupd2);
66 writel(ddrc_regs_val->addrmap0, &ddrc_regs->addrmap0);
67 writel(ddrc_regs_val->addrmap1, &ddrc_regs->addrmap1);
68 writel(ddrc_regs_val->addrmap4, &ddrc_regs->addrmap4);
69 writel(ddrc_regs_val->addrmap5, &ddrc_regs->addrmap5);
70 writel(ddrc_regs_val->addrmap6, &ddrc_regs->addrmap6);
71 writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg);
72 writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap);
73
74 /* De-assert DDR Controller preset and DDR PHY reset */
75 clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK);
76
77 /* PHY configuration */
78 writel(ddr_phy_regs_val->phy_con0, &ddr_phy_regs->phy_con0);
79 writel(ddr_phy_regs_val->phy_con1, &ddr_phy_regs->phy_con1);
80 writel(ddr_phy_regs_val->phy_con4, &ddr_phy_regs->phy_con4);
81 writel(ddr_phy_regs_val->mdll_con0, &ddr_phy_regs->mdll_con0);
82 writel(ddr_phy_regs_val->drvds_con0, &ddr_phy_regs->drvds_con0);
83 writel(ddr_phy_regs_val->offset_wr_con0, &ddr_phy_regs->offset_wr_con0);
84 writel(ddr_phy_regs_val->offset_rd_con0, &ddr_phy_regs->offset_rd_con0);
85 writel(ddr_phy_regs_val->cmd_sdll_con0 |
86 DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
87 &ddr_phy_regs->cmd_sdll_con0);
88 writel(ddr_phy_regs_val->cmd_sdll_con0 &
89 ~DDR_PHY_CMD_SDLL_CON0_CTRL_RESYNC_MASK,
90 &ddr_phy_regs->cmd_sdll_con0);
91 writel(ddr_phy_regs_val->offset_lp_con0, &ddr_phy_regs->offset_lp_con0);
92
93 /* calibration */
94 for (i = 0; i < calib_param->num_val; i++)
95 writel(calib_param->values[i], &ddr_phy_regs->zq_con0);
96
97 /* Wake_up DDR PHY */
98 HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_N_N);
99 writel(IOMUXC_GPR_GPR8_ddr_phy_ctrl_wake_up(0xf) |
100 IOMUXC_GPR_GPR8_ddr_phy_dfi_init_start_MASK,
101 &iomuxc_gpr_regs->gpr[8]);
102 HW_CCM_CCGR_WR(CCGR_IDX_DDR, CCM_CLK_ON_R_W);
103}
104
105/*
106 * Routine: imx_ddr_size
107 * Description: extract the current DRAM size from the DDRC registers
108 *
109 * @return: DRAM size
110 */
111unsigned int imx_ddr_size(void)
112{
113 struct ddrc *const ddrc_regs = (struct ddrc *)DDRC_IPS_BASE_ADDR;
114 u32 reg_val, field_val;
115 int bits = 0;/* Number of address bits */
116
117 /* Count data bus width bits */
118 reg_val = readl(&ddrc_regs->mstr);
119 field_val = (reg_val & MSTR_DATA_BUS_WIDTH_MASK) >> MSTR_DATA_BUS_WIDTH_SHIFT;
120 bits += 2 - field_val;
121 /* Count rank address bits */
122 field_val = (reg_val & MSTR_DATA_ACTIVE_RANKS_MASK) >> MSTR_DATA_ACTIVE_RANKS_SHIFT;
123 if (field_val > 1)
124 bits += field_val - 1;
125 /* Count column address bits */
126 bits += 2;/* Column address 0 and 1 are fixed mapped */
127 reg_val = readl(&ddrc_regs->addrmap2);
128 field_val = (reg_val & ADDRMAP2_COL_B2_MASK) >> ADDRMAP2_COL_B2_SHIFT;
129 if (field_val <= 7)
130 bits++;
131 field_val = (reg_val & ADDRMAP2_COL_B3_MASK) >> ADDRMAP2_COL_B3_SHIFT;
132 if (field_val <= 7)
133 bits++;
134 field_val = (reg_val & ADDRMAP2_COL_B4_MASK) >> ADDRMAP2_COL_B4_SHIFT;
135 if (field_val <= 7)
136 bits++;
137 field_val = (reg_val & ADDRMAP2_COL_B5_MASK) >> ADDRMAP2_COL_B5_SHIFT;
138 if (field_val <= 7)
139 bits++;
140 reg_val = readl(&ddrc_regs->addrmap3);
141 field_val = (reg_val & ADDRMAP3_COL_B6_MASK) >> ADDRMAP3_COL_B6_SHIFT;
142 if (field_val <= 7)
143 bits++;
144 field_val = (reg_val & ADDRMAP3_COL_B7_MASK) >> ADDRMAP3_COL_B7_SHIFT;
145 if (field_val <= 7)
146 bits++;
147 field_val = (reg_val & ADDRMAP3_COL_B8_MASK) >> ADDRMAP3_COL_B8_SHIFT;
148 if (field_val <= 7)
149 bits++;
150 field_val = (reg_val & ADDRMAP3_COL_B9_MASK) >> ADDRMAP3_COL_B9_SHIFT;
151 if (field_val <= 7)
152 bits++;
153 reg_val = readl(&ddrc_regs->addrmap4);
154 field_val = (reg_val & ADDRMAP4_COL_B10_MASK) >> ADDRMAP4_COL_B10_SHIFT;
155 if (field_val <= 7)
156 bits++;
157 field_val = (reg_val & ADDRMAP4_COL_B11_MASK) >> ADDRMAP4_COL_B11_SHIFT;
158 if (field_val <= 7)
159 bits++;
160 /* Count row address bits */
161 reg_val = readl(&ddrc_regs->addrmap5);
162 field_val = (reg_val & ADDRMAP5_ROW_B0_MASK) >> ADDRMAP5_ROW_B0_SHIFT;
163 if (field_val <= 11)
164 bits++;
165 field_val = (reg_val & ADDRMAP5_ROW_B1_MASK) >> ADDRMAP5_ROW_B1_SHIFT;
166 if (field_val <= 11)
167 bits++;
168 field_val = (reg_val & ADDRMAP5_ROW_B2_10_MASK) >> ADDRMAP5_ROW_B2_10_SHIFT;
169 if (field_val <= 11)
170 bits += 9;
171 field_val = (reg_val & ADDRMAP5_ROW_B11_MASK) >> ADDRMAP5_ROW_B11_SHIFT;
172 if (field_val <= 11)
173 bits++;
174 reg_val = readl(&ddrc_regs->addrmap6);
175 field_val = (reg_val & ADDRMAP6_ROW_B12_MASK) >> ADDRMAP6_ROW_B12_SHIFT;
176 if (field_val <= 11)
177 bits++;
178 field_val = (reg_val & ADDRMAP6_ROW_B13_MASK) >> ADDRMAP6_ROW_B13_SHIFT;
179 if (field_val <= 11)
180 bits++;
181 field_val = (reg_val & ADDRMAP6_ROW_B14_MASK) >> ADDRMAP6_ROW_B14_SHIFT;
182 if (field_val <= 11)
183 bits++;
184 field_val = (reg_val & ADDRMAP6_ROW_B15_MASK) >> ADDRMAP6_ROW_B15_SHIFT;
185 if (field_val <= 11)
186 bits++;
187 /* Count bank bits */
188 reg_val = readl(&ddrc_regs->addrmap1);
189 field_val = (reg_val & ADDRMAP1_BANK_B0_MASK) >> ADDRMAP1_BANK_B0_SHIFT;
190 if (field_val <= 30)
191 bits++;
192 field_val = (reg_val & ADDRMAP1_BANK_B1_MASK) >> ADDRMAP1_BANK_B1_SHIFT;
193 if (field_val <= 30)
194 bits++;
195 field_val = (reg_val & ADDRMAP1_BANK_B2_MASK) >> ADDRMAP1_BANK_B2_SHIFT;
196 if (field_val <= 29)
197 bits++;
198
Marcel Ziswiler21d69562018-09-19 13:01:55 +0200[diff] [blame]199 /* cap to max 2 GB */
200 if (bits > 31)
201 bits = 31;
202
Uri Mashiachdd587fa2017-09-24 09:00:23 +0300[diff] [blame]203 return 1 << bits;
204}