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git01.mediatek.com / filogic / uboot / 1400086402fc04370e2bccc441d14c5c2c4b748b / . / include / dm / uclass-id.h
blob: b993fc0a0639c87868c4c8e879d92a23d22e1eab [file] [log] [blame]
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]1/*
2 * Copyright (c) 2013 Google, Inc
3 *
4 * (C) Copyright 2012
5 * Pavel Herrmann <morpheus.ibis@gmail.com>
6 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9
10#ifndef _DM_UCLASS_ID_H
11#define _DM_UCLASS_ID_H
12
13/* TODO(sjg@chromium.org): this could be compile-time generated */
14enum uclass_id {
15 /* These are used internally by driver model */
16 UCLASS_ROOT = 0,
17 UCLASS_DEMO,
18 UCLASS_TEST,
19 UCLASS_TEST_FDT,
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]20 UCLASS_TEST_BUS,
Simon Glass10a4a332014-10-13 23:41:53 -0600[diff] [blame]21 UCLASS_SPI_EMUL, /* sandbox SPI device emulator */
Simon Glassdaa54702014-12-10 08:55:49 -0700[diff] [blame]22 UCLASS_I2C_EMUL, /* sandbox I2C device emulator */
Simon Glassd9e90bb2015-03-05 12:25:28 -0700[diff] [blame]23 UCLASS_PCI_EMUL, /* sandbox PCI device emulator */
Simon Glass59d66d22015-03-25 12:22:37 -0600[diff] [blame]24 UCLASS_USB_EMUL, /* sandbox USB bus device emulator */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]25 UCLASS_SIMPLE_BUS, /* bus with child devices */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]26
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]27 /* U-Boot uclasses start here - in alphabetical order */
28 UCLASS_CPU, /* CPU, typically part of an SoC */
29 UCLASS_CROS_EC, /* Chrome OS EC */
Simon Glass06679ad2015-04-14 21:03:38 -0600[diff] [blame]30 UCLASS_DISPLAY_PORT, /* Display port video */
Simon Glass3a2f3bd2015-06-23 15:39:04 -0600[diff] [blame]31 UCLASS_RAM, /* RAM controller */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]32 UCLASS_ETH, /* Ethernet device */
Simon Glasscebcebb2014-07-23 06:55:17 -0600[diff] [blame]33 UCLASS_GPIO, /* Bank of general-purpose I/O pins */
Simon Glassc7a58902014-12-10 08:55:47 -0700[diff] [blame]34 UCLASS_I2C, /* I2C bus */
Simon Glass6ca4ba02014-12-10 08:55:54 -0700[diff] [blame]35 UCLASS_I2C_EEPROM, /* I2C EEPROM device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]36 UCLASS_I2C_GENERIC, /* Generic I2C device */
Simon Glasscce3aed2015-06-23 15:38:45 -0600[diff] [blame]37 UCLASS_LED, /* Light-emitting diode (LED) */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]38 UCLASS_LPC, /* x86 'low pin count' interface */
39 UCLASS_MASS_STORAGE, /* Mass storage device */
Simon Glass1e8eb1b2015-06-23 15:38:48 -0600[diff] [blame]40 UCLASS_MMC, /* SD / MMC card or chip */
Ruchika Gupta98ebb122015-01-23 16:01:52 +0530[diff] [blame]41 UCLASS_MOD_EXP, /* RSA Mod Exp device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]42 UCLASS_PCH, /* x86 platform controller hub */
Simon Glassb94dc892015-03-05 12:25:25 -0700[diff] [blame]43 UCLASS_PCI, /* PCI bus */
44 UCLASS_PCI_GENERIC, /* Generic PCI bus device */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]45 UCLASS_PMIC, /* PMIC I/O device */
46 UCLASS_REGULATOR, /* Regulator device */
Simon Glass14000862015-06-23 15:39:13 -0600[diff] [blame^]47 UCLASS_RESET, /* Reset device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]48 UCLASS_RTC, /* Real time clock device */
49 UCLASS_SERIAL, /* Serial UART */
50 UCLASS_SPI, /* SPI bus */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]51 UCLASS_SPI_FLASH, /* SPI flash */
Simon Glass682ae862015-05-22 15:42:14 -0600[diff] [blame]52 UCLASS_SPI_GENERIC, /* Generic SPI flash target */
Simon Glass6a84aaf2015-06-23 15:38:43 -0600[diff] [blame]53 UCLASS_SYSCON, /* System configuration device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]54 UCLASS_THERMAL, /* Thermal sensor */
Simon Glass9b82eeb2015-03-25 12:21:59 -0600[diff] [blame]55 UCLASS_USB, /* USB bus */
Simon Glassc79173e2015-03-25 12:22:31 -0600[diff] [blame]56 UCLASS_USB_DEV_GENERIC, /* USB generic device */
Simon Glass10d8904f2015-04-14 21:03:19 -0600[diff] [blame]57 UCLASS_USB_HUB, /* USB hub */
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]58
Simon Glassdd6ab882014-02-26 15:59:18 -0700[diff] [blame]59 UCLASS_COUNT,
60 UCLASS_INVALID = -1,
61};
62
63#endif