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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk591dda52002-11-18 00:14:45 +00002/*
Graeme Russ45fc1d82011-04-13 19:43:26 +10003 * (C) Copyright 2008-2011
4 * Graeme Russ, <graeme.russ@gmail.com>
5 *
wdenk591dda52002-11-18 00:14:45 +00006 * (C) Copyright 2002
Albert ARIBAUD60fbc8d2011-08-04 18:45:45 +02007 * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
wdenk57b2d802003-06-27 21:31:46 +00008 *
wdenk591dda52002-11-18 00:14:45 +00009 * (C) Copyright 2002
10 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
11 * Marius Groeger <mgroeger@sysgo.de>
12 *
13 * (C) Copyright 2002
14 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
15 * Alex Zuepke <azu@sysgo.de>
16 *
Bin Meng035c1d22014-11-09 22:18:56 +080017 * Part of this file is adapted from coreboot
18 * src/arch/x86/lib/cpu.c
wdenk591dda52002-11-18 00:14:45 +000019 */
20
wdenk591dda52002-11-18 00:14:45 +000021#include <common.h>
Simon Glass5c2aabf2019-09-25 08:56:32 -060022#include <acpi_s3.h>
wdenk591dda52002-11-18 00:14:45 +000023#include <command.h>
Simon Glass1d91ba72019-11-14 12:57:37 -070024#include <cpu_func.h>
Bin Mengf967f9a2015-06-17 11:15:36 +080025#include <dm.h>
Simon Glass463fac22014-10-10 08:21:55 -060026#include <errno.h>
27#include <malloc.h>
Bin Menga4559642016-06-08 05:07:38 -070028#include <syscon.h>
Bin Mengac630252018-07-18 21:42:15 -070029#include <asm/acpi.h>
Bin Meng710d2152017-04-21 07:24:37 -070030#include <asm/acpi_table.h>
Stefan Reinauer2acf8482012-12-02 04:49:50 +000031#include <asm/control_regs.h>
Bin Meng1c9da372016-05-11 07:45:01 -070032#include <asm/coreboot_tables.h>
Simon Glass463fac22014-10-10 08:21:55 -060033#include <asm/cpu.h>
Bin Mengf967f9a2015-06-17 11:15:36 +080034#include <asm/lapic.h>
Simon Glass8dda5872016-03-11 22:07:11 -070035#include <asm/microcode.h>
Bin Mengf967f9a2015-06-17 11:15:36 +080036#include <asm/mp.h>
Bin Meng1141fcf2016-05-11 07:45:00 -070037#include <asm/mrccache.h>
Bin Mengc45a93b2015-07-06 16:31:30 +080038#include <asm/msr.h>
39#include <asm/mtrr.h>
Simon Glass9f0afe72014-11-12 22:42:26 -070040#include <asm/post.h>
Graeme Russ25391d12011-02-12 15:11:30 +110041#include <asm/processor.h>
Graeme Russ93efcb22011-02-12 15:11:32 +110042#include <asm/processor-flags.h>
Graeme Russ278638d2008-12-07 10:29:02 +110043#include <asm/interrupt.h>
Bin Mengf17cea62015-04-24 18:10:04 +080044#include <asm/tables.h>
Gabe Black6ed18882011-11-16 23:32:50 +000045#include <linux/compiler.h>
wdenk591dda52002-11-18 00:14:45 +000046
Bin Meng035c1d22014-11-09 22:18:56 +080047DECLARE_GLOBAL_DATA_PTR;
48
Simon Glassdd45a7a2019-12-06 21:41:51 -070049#ifndef CONFIG_TPL_BUILD
Bin Meng035c1d22014-11-09 22:18:56 +080050static const char *const x86_vendor_name[] = {
51 [X86_VENDOR_INTEL] = "Intel",
52 [X86_VENDOR_CYRIX] = "Cyrix",
53 [X86_VENDOR_AMD] = "AMD",
54 [X86_VENDOR_UMC] = "UMC",
55 [X86_VENDOR_NEXGEN] = "NexGen",
56 [X86_VENDOR_CENTAUR] = "Centaur",
57 [X86_VENDOR_RISE] = "Rise",
58 [X86_VENDOR_TRANSMETA] = "Transmeta",
59 [X86_VENDOR_NSC] = "NSC",
60 [X86_VENDOR_SIS] = "SiS",
61};
Simon Glassdd45a7a2019-12-06 21:41:51 -070062#endif
Bin Meng035c1d22014-11-09 22:18:56 +080063
Gabe Black846d08e2012-10-20 12:33:10 +000064int __weak x86_cleanup_before_linux(void)
65{
Simon Glassbcc28da2013-04-17 16:13:35 +000066#ifdef CONFIG_BOOTSTAGE_STASH
Simon Glass5322d622015-03-02 17:04:37 -070067 bootstage_stash((void *)CONFIG_BOOTSTAGE_STASH_ADDR,
Simon Glassbcc28da2013-04-17 16:13:35 +000068 CONFIG_BOOTSTAGE_STASH_SIZE);
69#endif
70
Gabe Black846d08e2012-10-20 12:33:10 +000071 return 0;
72}
73
Graeme Russ6e256002011-12-27 22:46:43 +110074int x86_init_cache(void)
75{
76 enable_caches();
77
wdenk591dda52002-11-18 00:14:45 +000078 return 0;
79}
Graeme Russ6e256002011-12-27 22:46:43 +110080int init_cache(void) __attribute__((weak, alias("x86_init_cache")));
wdenk591dda52002-11-18 00:14:45 +000081
Graeme Russfdee8b12011-11-08 02:33:13 +000082void flush_cache(unsigned long dummy1, unsigned long dummy2)
wdenk591dda52002-11-18 00:14:45 +000083{
84 asm("wbinvd\n");
wdenk591dda52002-11-18 00:14:45 +000085}
Graeme Russ278638d2008-12-07 10:29:02 +110086
Stefan Reinauer2acf8482012-12-02 04:49:50 +000087/* Define these functions to allow ehch-hcd to function */
88void flush_dcache_range(unsigned long start, unsigned long stop)
89{
90}
91
92void invalidate_dcache_range(unsigned long start, unsigned long stop)
93{
94}
Simon Glass2baa3bb2013-02-28 19:26:11 +000095
96void dcache_enable(void)
97{
98 enable_caches();
99}
100
101void dcache_disable(void)
102{
103 disable_caches();
104}
105
106void icache_enable(void)
107{
108}
109
110void icache_disable(void)
111{
112}
113
114int icache_status(void)
115{
116 return 1;
117}
Simon Glassd8d9fec2014-10-10 08:21:52 -0600118
Simon Glassdd45a7a2019-12-06 21:41:51 -0700119#ifndef CONFIG_TPL_BUILD
Bin Meng035c1d22014-11-09 22:18:56 +0800120const char *cpu_vendor_name(int vendor)
121{
122 const char *name;
123 name = "<invalid cpu vendor>";
Heinrich Schuchardt5e5fe802017-11-20 19:45:56 +0100124 if (vendor < ARRAY_SIZE(x86_vendor_name) &&
125 x86_vendor_name[vendor])
Bin Meng035c1d22014-11-09 22:18:56 +0800126 name = x86_vendor_name[vendor];
Simon Glass2f2efbc2014-10-10 08:21:54 -0600127
Bin Meng035c1d22014-11-09 22:18:56 +0800128 return name;
Simon Glass2f2efbc2014-10-10 08:21:54 -0600129}
Simon Glassdd45a7a2019-12-06 21:41:51 -0700130#endif
Simon Glass2f2efbc2014-10-10 08:21:54 -0600131
Simon Glass543bb142014-11-10 18:00:26 -0700132char *cpu_get_name(char *name)
Simon Glass2f2efbc2014-10-10 08:21:54 -0600133{
Simon Glass543bb142014-11-10 18:00:26 -0700134 unsigned int *name_as_ints = (unsigned int *)name;
Bin Meng035c1d22014-11-09 22:18:56 +0800135 struct cpuid_result regs;
Simon Glass543bb142014-11-10 18:00:26 -0700136 char *ptr;
Bin Meng035c1d22014-11-09 22:18:56 +0800137 int i;
Simon Glass2f2efbc2014-10-10 08:21:54 -0600138
Simon Glass543bb142014-11-10 18:00:26 -0700139 /* This bit adds up to 48 bytes */
Bin Meng035c1d22014-11-09 22:18:56 +0800140 for (i = 0; i < 3; i++) {
141 regs = cpuid(0x80000002 + i);
142 name_as_ints[i * 4 + 0] = regs.eax;
143 name_as_ints[i * 4 + 1] = regs.ebx;
144 name_as_ints[i * 4 + 2] = regs.ecx;
145 name_as_ints[i * 4 + 3] = regs.edx;
146 }
Simon Glass543bb142014-11-10 18:00:26 -0700147 name[CPU_MAX_NAME_LEN - 1] = '\0';
Simon Glass2f2efbc2014-10-10 08:21:54 -0600148
Bin Meng035c1d22014-11-09 22:18:56 +0800149 /* Skip leading spaces. */
Simon Glass543bb142014-11-10 18:00:26 -0700150 ptr = name;
151 while (*ptr == ' ')
152 ptr++;
Bin Meng035c1d22014-11-09 22:18:56 +0800153
Simon Glass543bb142014-11-10 18:00:26 -0700154 return ptr;
Simon Glass2f2efbc2014-10-10 08:21:54 -0600155}
156
Simon Glass543bb142014-11-10 18:00:26 -0700157int default_print_cpuinfo(void)
Simon Glass2f2efbc2014-10-10 08:21:54 -0600158{
Bin Meng035c1d22014-11-09 22:18:56 +0800159 printf("CPU: %s, vendor %s, device %xh\n",
160 cpu_has_64bit() ? "x86_64" : "x86",
161 cpu_vendor_name(gd->arch.x86_vendor), gd->arch.x86_device);
Simon Glass2f2efbc2014-10-10 08:21:54 -0600162
Bin Mengef61f772017-04-21 07:24:32 -0700163#ifdef CONFIG_HAVE_ACPI_RESUME
164 debug("ACPI previous sleep state: %s\n",
165 acpi_ss_string(gd->arch.prev_sleep_state));
166#endif
167
Simon Glass2f2efbc2014-10-10 08:21:54 -0600168 return 0;
169}
Simon Glass463fac22014-10-10 08:21:55 -0600170
Simon Glass9f0afe72014-11-12 22:42:26 -0700171void show_boot_progress(int val)
172{
Simon Glass9f0afe72014-11-12 22:42:26 -0700173 outb(val, POST_PORT);
174}
Bin Mengf17cea62015-04-24 18:10:04 +0800175
Bin Mengdb59dd32018-06-17 05:57:53 -0700176#if !defined(CONFIG_SYS_COREBOOT) && !defined(CONFIG_EFI_STUB)
Bin Meng2f8560c2016-05-11 07:44:56 -0700177/*
178 * Implement a weak default function for boards that optionally
179 * need to clean up the system before jumping to the kernel.
180 */
181__weak void board_final_cleanup(void)
182{
183}
184
Bin Mengf17cea62015-04-24 18:10:04 +0800185int last_stage_init(void)
186{
Bin Meng467f4112018-07-18 21:42:16 -0700187 struct acpi_fadt __maybe_unused *fadt;
188
Bin Meng159661d2017-04-21 07:24:41 -0700189 board_final_cleanup();
190
Bin Meng467f4112018-07-18 21:42:16 -0700191#ifdef CONFIG_HAVE_ACPI_RESUME
192 fadt = acpi_find_fadt();
Bin Meng710d2152017-04-21 07:24:37 -0700193
Bin Meng467f4112018-07-18 21:42:16 -0700194 if (fadt && gd->arch.prev_sleep_state == ACPI_S3)
Bin Meng280aebe2017-04-21 07:24:44 -0700195 acpi_resume(fadt);
Bin Meng710d2152017-04-21 07:24:37 -0700196#endif
197
Bin Mengf17cea62015-04-24 18:10:04 +0800198 write_tables();
199
Bin Meng467f4112018-07-18 21:42:16 -0700200#ifdef CONFIG_GENERATE_ACPI_TABLE
201 fadt = acpi_find_fadt();
202
203 /* Don't touch ACPI hardware on HW reduced platforms */
204 if (fadt && !(fadt->flags & ACPI_FADT_HW_REDUCED_ACPI)) {
205 /*
206 * Other than waiting for OSPM to request us to switch to ACPI
207 * mode, do it by ourselves, since SMI will not be triggered.
208 */
209 enter_acpi_mode(fadt->pm1a_cnt_blk);
210 }
211#endif
212
Bin Mengf17cea62015-04-24 18:10:04 +0800213 return 0;
214}
215#endif
Simon Glass02fe5e62015-04-29 22:26:01 -0600216
Simon Glass0aa7bfa2016-01-17 16:11:28 -0700217static int x86_init_cpus(void)
Simon Glass02fe5e62015-04-29 22:26:01 -0600218{
Bin Mengf967f9a2015-06-17 11:15:36 +0800219#ifdef CONFIG_SMP
220 debug("Init additional CPUs\n");
221 x86_mp_init();
Bin Meng89727762015-07-22 01:21:12 -0700222#else
223 struct udevice *dev;
224
225 /*
226 * This causes the cpu-x86 driver to be probed.
227 * We don't check return value here as we want to allow boards
228 * which have not been converted to use cpu uclass driver to boot.
229 */
230 uclass_first_device(UCLASS_CPU, &dev);
Bin Mengf967f9a2015-06-17 11:15:36 +0800231#endif
232
Simon Glass02fe5e62015-04-29 22:26:01 -0600233 return 0;
234}
235
236int cpu_init_r(void)
237{
Simon Glass00431f62016-01-17 16:11:30 -0700238 struct udevice *dev;
239 int ret;
240
241 if (!ll_boot_init())
242 return 0;
243
244 ret = x86_init_cpus();
245 if (ret)
246 return ret;
247
248 /*
249 * Set up the northbridge, PCH and LPC if available. Note that these
250 * may have had some limited pre-relocation init if they were probed
251 * before relocation, but this is post relocation.
252 */
253 uclass_first_device(UCLASS_NORTHBRIDGE, &dev);
254 uclass_first_device(UCLASS_PCH, &dev);
255 uclass_first_device(UCLASS_LPC, &dev);
Simon Glass2b6d80b2015-08-04 12:34:00 -0600256
Bin Menga4559642016-06-08 05:07:38 -0700257 /* Set up pin control if available */
258 ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
259 debug("%s, pinctrl=%p, ret=%d\n", __func__, dev, ret);
260
Simon Glass2b6d80b2015-08-04 12:34:00 -0600261 return 0;
Simon Glass02fe5e62015-04-29 22:26:01 -0600262}
Bin Meng1141fcf2016-05-11 07:45:00 -0700263
264#ifndef CONFIG_EFI_STUB
265int reserve_arch(void)
266{
267#ifdef CONFIG_ENABLE_MRC_CACHE
Bin Meng1c9da372016-05-11 07:45:01 -0700268 mrccache_reserve();
269#endif
270
271#ifdef CONFIG_SEABIOS
272 high_table_reserve();
Bin Meng1141fcf2016-05-11 07:45:00 -0700273#endif
Bin Meng1c9da372016-05-11 07:45:01 -0700274
Bin Meng353f5cb2017-04-21 07:24:47 -0700275#ifdef CONFIG_HAVE_ACPI_RESUME
276 acpi_s3_reserve();
277
278#ifdef CONFIG_HAVE_FSP
Bin Mengcf200302017-04-21 07:24:39 -0700279 /*
280 * Save stack address to CMOS so that at next S3 boot,
281 * we can use it as the stack address for fsp_contiue()
282 */
283 fsp_save_s3_stack();
Bin Meng353f5cb2017-04-21 07:24:47 -0700284#endif /* CONFIG_HAVE_FSP */
285#endif /* CONFIG_HAVE_ACPI_RESUME */
Bin Mengcf200302017-04-21 07:24:39 -0700286
Bin Meng1c9da372016-05-11 07:45:01 -0700287 return 0;
Bin Meng1141fcf2016-05-11 07:45:00 -0700288}
289#endif