developer | 13dc3c8 | 2020-10-16 11:38:39 +0800 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * mtu3_qmu.c - Queue Management Unit driver for device controller |
| 4 | * |
| 5 | * Copyright (C) 2016 MediaTek Inc. |
| 6 | * |
| 7 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| 8 | */ |
| 9 | |
| 10 | /* |
| 11 | * Queue Management Unit (QMU) is designed to unload SW effort |
| 12 | * to serve DMA interrupts. |
| 13 | * By preparing General Purpose Descriptor (GPD) and Buffer Descriptor (BD), |
| 14 | * SW links data buffers and triggers QMU to send / receive data to |
| 15 | * host / from device at a time. |
| 16 | * And now only GPD is supported. |
| 17 | * |
| 18 | * For more detailed information, please refer to QMU Programming Guide |
| 19 | */ |
| 20 | |
| 21 | #include <asm/cache.h> |
| 22 | #include <cpu_func.h> |
| 23 | #include <linux/iopoll.h> |
| 24 | #include <linux/types.h> |
| 25 | |
| 26 | #include "mtu3.h" |
| 27 | |
| 28 | #define QMU_CHECKSUM_LEN 16 |
| 29 | |
| 30 | #define GPD_FLAGS_HWO BIT(0) |
| 31 | #define GPD_FLAGS_BDP BIT(1) |
| 32 | #define GPD_FLAGS_BPS BIT(2) |
| 33 | #define GPD_FLAGS_IOC BIT(7) |
| 34 | |
| 35 | #define GPD_EXT_FLAG_ZLP BIT(5) |
| 36 | |
| 37 | #define DCACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE |
| 38 | |
| 39 | void mtu3_flush_cache(uintptr_t addr, u32 len) |
| 40 | { |
| 41 | WARN_ON(!(void *)addr || len == 0); |
| 42 | |
| 43 | flush_dcache_range(addr & ~(DCACHELINE_SIZE - 1), |
| 44 | ALIGN(addr + len, DCACHELINE_SIZE)); |
| 45 | } |
| 46 | |
| 47 | void mtu3_inval_cache(uintptr_t addr, u32 len) |
| 48 | { |
| 49 | WARN_ON(!(void *)addr || len == 0); |
| 50 | |
| 51 | invalidate_dcache_range(addr & ~(DCACHELINE_SIZE - 1), |
| 52 | ALIGN(addr + len, DCACHELINE_SIZE)); |
| 53 | } |
| 54 | |
| 55 | static struct qmu_gpd *gpd_dma_to_virt(struct mtu3_gpd_ring *ring, |
| 56 | dma_addr_t dma_addr) |
| 57 | { |
| 58 | dma_addr_t dma_base = ring->dma; |
| 59 | struct qmu_gpd *gpd_head = ring->start; |
| 60 | u32 offset = (dma_addr - dma_base) / sizeof(*gpd_head); |
| 61 | |
| 62 | if (offset >= MAX_GPD_NUM) |
| 63 | return NULL; |
| 64 | |
| 65 | return gpd_head + offset; |
| 66 | } |
| 67 | |
| 68 | static dma_addr_t gpd_virt_to_dma(struct mtu3_gpd_ring *ring, |
| 69 | struct qmu_gpd *gpd) |
| 70 | { |
| 71 | dma_addr_t dma_base = ring->dma; |
| 72 | struct qmu_gpd *gpd_head = ring->start; |
| 73 | u32 offset; |
| 74 | |
| 75 | offset = gpd - gpd_head; |
| 76 | if (offset >= MAX_GPD_NUM) |
| 77 | return 0; |
| 78 | |
| 79 | return dma_base + (offset * sizeof(*gpd)); |
| 80 | } |
| 81 | |
| 82 | static void gpd_ring_init(struct mtu3_gpd_ring *ring, struct qmu_gpd *gpd) |
| 83 | { |
| 84 | ring->start = gpd; |
| 85 | ring->enqueue = gpd; |
| 86 | ring->dequeue = gpd; |
| 87 | ring->end = gpd + MAX_GPD_NUM - 1; |
| 88 | } |
| 89 | |
| 90 | static void reset_gpd_list(struct mtu3_ep *mep) |
| 91 | { |
| 92 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 93 | struct qmu_gpd *gpd = ring->start; |
| 94 | |
| 95 | if (gpd) { |
| 96 | gpd->flag &= ~GPD_FLAGS_HWO; |
| 97 | gpd_ring_init(ring, gpd); |
| 98 | mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 99 | } |
| 100 | } |
| 101 | |
| 102 | int mtu3_gpd_ring_alloc(struct mtu3_ep *mep) |
| 103 | { |
| 104 | struct qmu_gpd *gpd; |
| 105 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 106 | |
| 107 | /* software own all gpds as default */ |
| 108 | gpd = memalign(DCACHELINE_SIZE, QMU_GPD_RING_SIZE); |
| 109 | if (!gpd) |
| 110 | return -ENOMEM; |
| 111 | |
| 112 | memset(gpd, 0, QMU_GPD_RING_SIZE); |
| 113 | ring->dma = (dma_addr_t)gpd; |
| 114 | gpd_ring_init(ring, gpd); |
| 115 | |
| 116 | return 0; |
| 117 | } |
| 118 | |
| 119 | void mtu3_gpd_ring_free(struct mtu3_ep *mep) |
| 120 | { |
| 121 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 122 | |
| 123 | kfree(ring->start); |
| 124 | memset(ring, 0, sizeof(*ring)); |
| 125 | } |
| 126 | |
| 127 | void mtu3_qmu_resume(struct mtu3_ep *mep) |
| 128 | { |
| 129 | struct mtu3 *mtu = mep->mtu; |
| 130 | void __iomem *mbase = mtu->mac_base; |
| 131 | int epnum = mep->epnum; |
| 132 | u32 offset; |
| 133 | |
| 134 | offset = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum); |
| 135 | |
| 136 | mtu3_writel(mbase, offset, QMU_Q_RESUME); |
| 137 | if (!(mtu3_readl(mbase, offset) & QMU_Q_ACTIVE)) |
| 138 | mtu3_writel(mbase, offset, QMU_Q_RESUME); |
| 139 | } |
| 140 | |
| 141 | static struct qmu_gpd *advance_enq_gpd(struct mtu3_gpd_ring *ring) |
| 142 | { |
| 143 | if (ring->enqueue < ring->end) |
| 144 | ring->enqueue++; |
| 145 | else |
| 146 | ring->enqueue = ring->start; |
| 147 | |
| 148 | return ring->enqueue; |
| 149 | } |
| 150 | |
| 151 | static struct qmu_gpd *advance_deq_gpd(struct mtu3_gpd_ring *ring) |
| 152 | { |
| 153 | if (ring->dequeue < ring->end) |
| 154 | ring->dequeue++; |
| 155 | else |
| 156 | ring->dequeue = ring->start; |
| 157 | |
| 158 | return ring->dequeue; |
| 159 | } |
| 160 | |
| 161 | /* check if a ring is emtpy */ |
| 162 | static int gpd_ring_empty(struct mtu3_gpd_ring *ring) |
| 163 | { |
| 164 | struct qmu_gpd *enq = ring->enqueue; |
| 165 | struct qmu_gpd *next; |
| 166 | |
| 167 | if (ring->enqueue < ring->end) |
| 168 | next = enq + 1; |
| 169 | else |
| 170 | next = ring->start; |
| 171 | |
| 172 | /* one gpd is reserved to simplify gpd preparation */ |
| 173 | return next == ring->dequeue; |
| 174 | } |
| 175 | |
| 176 | int mtu3_prepare_transfer(struct mtu3_ep *mep) |
| 177 | { |
| 178 | return gpd_ring_empty(&mep->gpd_ring); |
| 179 | } |
| 180 | |
| 181 | static int mtu3_prepare_tx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq) |
| 182 | { |
| 183 | struct qmu_gpd *enq; |
| 184 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 185 | struct qmu_gpd *gpd = ring->enqueue; |
| 186 | struct usb_request *req = &mreq->request; |
| 187 | |
| 188 | /* set all fields to zero as default value */ |
| 189 | memset(gpd, 0, sizeof(*gpd)); |
| 190 | |
| 191 | gpd->buffer = cpu_to_le32((u32)req->dma); |
| 192 | gpd->buf_len = cpu_to_le16(req->length); |
| 193 | |
| 194 | /* get the next GPD */ |
| 195 | enq = advance_enq_gpd(ring); |
| 196 | dev_dbg(mep->mtu->dev, "TX-EP%d queue gpd=%p, enq=%p\n", |
| 197 | mep->epnum, gpd, enq); |
| 198 | |
| 199 | enq->flag &= ~GPD_FLAGS_HWO; |
| 200 | gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq)); |
| 201 | |
| 202 | if (req->zero) |
| 203 | gpd->ext_flag |= GPD_EXT_FLAG_ZLP; |
| 204 | |
| 205 | gpd->flag |= GPD_FLAGS_IOC | GPD_FLAGS_HWO; |
| 206 | |
| 207 | mreq->gpd = gpd; |
| 208 | |
| 209 | if (req->length) |
| 210 | mtu3_flush_cache((uintptr_t)req->buf, req->length); |
| 211 | |
| 212 | mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 213 | |
| 214 | return 0; |
| 215 | } |
| 216 | |
| 217 | static int mtu3_prepare_rx_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq) |
| 218 | { |
| 219 | struct qmu_gpd *enq; |
| 220 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 221 | struct qmu_gpd *gpd = ring->enqueue; |
| 222 | struct usb_request *req = &mreq->request; |
| 223 | |
| 224 | /* set all fields to zero as default value */ |
| 225 | memset(gpd, 0, sizeof(*gpd)); |
| 226 | |
| 227 | gpd->buffer = cpu_to_le32((u32)req->dma); |
| 228 | gpd->data_buf_len = cpu_to_le16(req->length); |
| 229 | |
| 230 | /* get the next GPD */ |
| 231 | enq = advance_enq_gpd(ring); |
| 232 | dev_dbg(mep->mtu->dev, "RX-EP%d queue gpd=%p, enq=%p\n", |
| 233 | mep->epnum, gpd, enq); |
| 234 | |
| 235 | enq->flag &= ~GPD_FLAGS_HWO; |
| 236 | gpd->next_gpd = cpu_to_le32((u32)gpd_virt_to_dma(ring, enq)); |
| 237 | gpd->flag |= GPD_FLAGS_IOC | GPD_FLAGS_HWO; |
| 238 | |
| 239 | mreq->gpd = gpd; |
| 240 | |
| 241 | mtu3_inval_cache((uintptr_t)req->buf, req->length); |
| 242 | mtu3_flush_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 243 | |
| 244 | return 0; |
| 245 | } |
| 246 | |
| 247 | void mtu3_insert_gpd(struct mtu3_ep *mep, struct mtu3_request *mreq) |
| 248 | { |
| 249 | if (mep->is_in) |
| 250 | mtu3_prepare_tx_gpd(mep, mreq); |
| 251 | else |
| 252 | mtu3_prepare_rx_gpd(mep, mreq); |
| 253 | } |
| 254 | |
| 255 | int mtu3_qmu_start(struct mtu3_ep *mep) |
| 256 | { |
| 257 | struct mtu3 *mtu = mep->mtu; |
| 258 | void __iomem *mbase = mtu->mac_base; |
| 259 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 260 | u8 epnum = mep->epnum; |
| 261 | |
| 262 | if (mep->is_in) { |
| 263 | /* set QMU start address */ |
| 264 | mtu3_writel(mbase, USB_QMU_TQSAR(epnum), ring->dma); |
| 265 | mtu3_setbits(mbase, MU3D_EP_TXCR0(epnum), TX_DMAREQEN); |
| 266 | /* send zero length packet according to ZLP flag in GPD */ |
| 267 | mtu3_setbits(mbase, U3D_QCR1, QMU_TX_ZLP(epnum)); |
| 268 | mtu3_writel(mbase, U3D_TQERRIESR0, |
| 269 | QMU_TX_LEN_ERR(epnum) | QMU_TX_CS_ERR(epnum)); |
| 270 | |
| 271 | if (mtu3_readl(mbase, USB_QMU_TQCSR(epnum)) & QMU_Q_ACTIVE) { |
| 272 | dev_warn(mtu->dev, "Tx %d Active Now!\n", epnum); |
| 273 | return 0; |
| 274 | } |
| 275 | mtu3_writel(mbase, USB_QMU_TQCSR(epnum), QMU_Q_START); |
| 276 | |
| 277 | } else { |
| 278 | mtu3_writel(mbase, USB_QMU_RQSAR(epnum), ring->dma); |
| 279 | mtu3_setbits(mbase, MU3D_EP_RXCR0(epnum), RX_DMAREQEN); |
| 280 | /* don't expect ZLP */ |
| 281 | mtu3_clrbits(mbase, U3D_QCR3, QMU_RX_ZLP(epnum)); |
| 282 | /* move to next GPD when receive ZLP */ |
| 283 | mtu3_setbits(mbase, U3D_QCR3, QMU_RX_COZ(epnum)); |
| 284 | mtu3_writel(mbase, U3D_RQERRIESR0, |
| 285 | QMU_RX_LEN_ERR(epnum) | QMU_RX_CS_ERR(epnum)); |
| 286 | mtu3_writel(mbase, U3D_RQERRIESR1, QMU_RX_ZLP_ERR(epnum)); |
| 287 | |
| 288 | if (mtu3_readl(mbase, USB_QMU_RQCSR(epnum)) & QMU_Q_ACTIVE) { |
| 289 | dev_warn(mtu->dev, "Rx %d Active Now!\n", epnum); |
| 290 | return 0; |
| 291 | } |
| 292 | mtu3_writel(mbase, USB_QMU_RQCSR(epnum), QMU_Q_START); |
| 293 | } |
| 294 | |
| 295 | return 0; |
| 296 | } |
| 297 | |
| 298 | /* may called in atomic context */ |
| 299 | void mtu3_qmu_stop(struct mtu3_ep *mep) |
| 300 | { |
| 301 | struct mtu3 *mtu = mep->mtu; |
| 302 | void __iomem *mbase = mtu->mac_base; |
| 303 | int epnum = mep->epnum; |
| 304 | u32 value = 0; |
| 305 | u32 qcsr; |
| 306 | int ret; |
| 307 | |
| 308 | qcsr = mep->is_in ? USB_QMU_TQCSR(epnum) : USB_QMU_RQCSR(epnum); |
| 309 | |
| 310 | if (!(mtu3_readl(mbase, qcsr) & QMU_Q_ACTIVE)) { |
| 311 | dev_dbg(mtu->dev, "%s's qmu is inactive now!\n", mep->name); |
| 312 | return; |
| 313 | } |
| 314 | mtu3_writel(mbase, qcsr, QMU_Q_STOP); |
| 315 | |
| 316 | ret = readl_poll_timeout(mbase + qcsr, value, |
| 317 | !(value & QMU_Q_ACTIVE), 1000); |
| 318 | if (ret) { |
| 319 | dev_err(mtu->dev, "stop %s's qmu failed\n", mep->name); |
| 320 | return; |
| 321 | } |
| 322 | |
| 323 | dev_dbg(mtu->dev, "%s's qmu stop now!\n", mep->name); |
| 324 | } |
| 325 | |
| 326 | void mtu3_qmu_flush(struct mtu3_ep *mep) |
| 327 | { |
| 328 | dev_dbg(mep->mtu->dev, "%s flush QMU %s\n", __func__, |
| 329 | ((mep->is_in) ? "TX" : "RX")); |
| 330 | |
| 331 | /*Stop QMU */ |
| 332 | mtu3_qmu_stop(mep); |
| 333 | reset_gpd_list(mep); |
| 334 | } |
| 335 | |
| 336 | /* |
| 337 | * NOTE: request list maybe is already empty as following case: |
| 338 | * queue_tx --> qmu_interrupt(clear interrupt pending, schedule tasklet)--> |
| 339 | * queue_tx --> process_tasklet(meanwhile, the second one is transferred, |
| 340 | * tasklet process both of them)-->qmu_interrupt for second one. |
| 341 | * To avoid upper case, put qmu_done_tx in ISR directly to process it. |
| 342 | */ |
| 343 | static void qmu_done_tx(struct mtu3 *mtu, u8 epnum) |
| 344 | { |
| 345 | struct mtu3_ep *mep = mtu->in_eps + epnum; |
| 346 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 347 | void __iomem *mbase = mtu->mac_base; |
| 348 | struct qmu_gpd *gpd = ring->dequeue; |
| 349 | struct qmu_gpd *gpd_current = NULL; |
| 350 | struct usb_request *req = NULL; |
| 351 | struct mtu3_request *mreq; |
| 352 | dma_addr_t cur_gpd_dma; |
| 353 | |
| 354 | /*transfer phy address got from QMU register to virtual address */ |
| 355 | cur_gpd_dma = mtu3_readl(mbase, USB_QMU_TQCPR(epnum)); |
| 356 | gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); |
| 357 | mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 358 | |
| 359 | dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n", |
| 360 | __func__, epnum, gpd, gpd_current, ring->enqueue); |
| 361 | |
| 362 | while (gpd != gpd_current && !(gpd->flag & GPD_FLAGS_HWO)) { |
| 363 | mreq = next_request(mep); |
| 364 | |
| 365 | if (!mreq || mreq->gpd != gpd) { |
| 366 | dev_err(mtu->dev, "no correct TX req is found\n"); |
| 367 | break; |
| 368 | } |
| 369 | |
| 370 | req = &mreq->request; |
| 371 | req->actual = le16_to_cpu(gpd->buf_len); |
| 372 | mtu3_req_complete(mep, req, 0); |
| 373 | |
| 374 | gpd = advance_deq_gpd(ring); |
| 375 | mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 376 | } |
| 377 | |
| 378 | dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n", |
| 379 | __func__, epnum, ring->dequeue, ring->enqueue); |
| 380 | } |
| 381 | |
| 382 | static void qmu_done_rx(struct mtu3 *mtu, u8 epnum) |
| 383 | { |
| 384 | struct mtu3_ep *mep = mtu->out_eps + epnum; |
| 385 | struct mtu3_gpd_ring *ring = &mep->gpd_ring; |
| 386 | void __iomem *mbase = mtu->mac_base; |
| 387 | struct qmu_gpd *gpd = ring->dequeue; |
| 388 | struct qmu_gpd *gpd_current = NULL; |
| 389 | struct usb_request *req = NULL; |
| 390 | struct mtu3_request *mreq; |
| 391 | dma_addr_t cur_gpd_dma; |
| 392 | |
| 393 | cur_gpd_dma = mtu3_readl(mbase, USB_QMU_RQCPR(epnum)); |
| 394 | gpd_current = gpd_dma_to_virt(ring, cur_gpd_dma); |
| 395 | mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 396 | |
| 397 | dev_dbg(mtu->dev, "%s EP%d, last=%p, current=%p, enq=%p\n", |
| 398 | __func__, epnum, gpd, gpd_current, ring->enqueue); |
| 399 | |
| 400 | while (gpd != gpd_current && !(gpd->flag & GPD_FLAGS_HWO)) { |
| 401 | mreq = next_request(mep); |
| 402 | |
| 403 | if (!mreq || mreq->gpd != gpd) { |
| 404 | dev_err(mtu->dev, "no correct RX req is found\n"); |
| 405 | break; |
| 406 | } |
| 407 | req = &mreq->request; |
| 408 | |
| 409 | req->actual = le16_to_cpu(gpd->buf_len); |
| 410 | mtu3_req_complete(mep, req, 0); |
| 411 | |
| 412 | gpd = advance_deq_gpd(ring); |
| 413 | mtu3_inval_cache((uintptr_t)gpd, sizeof(*gpd)); |
| 414 | } |
| 415 | |
| 416 | dev_dbg(mtu->dev, "%s EP%d, deq=%p, enq=%p, complete\n", |
| 417 | __func__, epnum, ring->dequeue, ring->enqueue); |
| 418 | } |
| 419 | |
| 420 | static void qmu_done_isr(struct mtu3 *mtu, u32 done_status) |
| 421 | { |
| 422 | int i; |
| 423 | |
| 424 | for (i = 1; i < mtu->num_eps; i++) { |
| 425 | if (done_status & QMU_RX_DONE_INT(i)) |
| 426 | qmu_done_rx(mtu, i); |
| 427 | if (done_status & QMU_TX_DONE_INT(i)) |
| 428 | qmu_done_tx(mtu, i); |
| 429 | } |
| 430 | } |
| 431 | |
| 432 | static void qmu_exception_isr(struct mtu3 *mtu, u32 qmu_status) |
| 433 | { |
| 434 | void __iomem *mbase = mtu->mac_base; |
| 435 | u32 errval; |
| 436 | int i; |
| 437 | |
| 438 | if ((qmu_status & RXQ_CSERR_INT) || (qmu_status & RXQ_LENERR_INT)) { |
| 439 | errval = mtu3_readl(mbase, U3D_RQERRIR0); |
| 440 | for (i = 1; i < mtu->num_eps; i++) { |
| 441 | if (errval & QMU_RX_CS_ERR(i)) |
| 442 | dev_err(mtu->dev, "Rx %d CS error!\n", i); |
| 443 | |
| 444 | if (errval & QMU_RX_LEN_ERR(i)) |
| 445 | dev_err(mtu->dev, "RX %d Length error\n", i); |
| 446 | } |
| 447 | mtu3_writel(mbase, U3D_RQERRIR0, errval); |
| 448 | } |
| 449 | |
| 450 | if (qmu_status & RXQ_ZLPERR_INT) { |
| 451 | errval = mtu3_readl(mbase, U3D_RQERRIR1); |
| 452 | for (i = 1; i < mtu->num_eps; i++) { |
| 453 | if (errval & QMU_RX_ZLP_ERR(i)) |
| 454 | dev_dbg(mtu->dev, "RX EP%d Recv ZLP\n", i); |
| 455 | } |
| 456 | mtu3_writel(mbase, U3D_RQERRIR1, errval); |
| 457 | } |
| 458 | |
| 459 | if ((qmu_status & TXQ_CSERR_INT) || (qmu_status & TXQ_LENERR_INT)) { |
| 460 | errval = mtu3_readl(mbase, U3D_TQERRIR0); |
| 461 | for (i = 1; i < mtu->num_eps; i++) { |
| 462 | if (errval & QMU_TX_CS_ERR(i)) |
| 463 | dev_err(mtu->dev, "Tx %d checksum error!\n", i); |
| 464 | |
| 465 | if (errval & QMU_TX_LEN_ERR(i)) |
| 466 | dev_err(mtu->dev, "Tx %d zlp error!\n", i); |
| 467 | } |
| 468 | mtu3_writel(mbase, U3D_TQERRIR0, errval); |
| 469 | } |
| 470 | } |
| 471 | |
| 472 | irqreturn_t mtu3_qmu_isr(struct mtu3 *mtu) |
| 473 | { |
| 474 | void __iomem *mbase = mtu->mac_base; |
| 475 | u32 qmu_status; |
| 476 | u32 qmu_done_status; |
| 477 | |
| 478 | /* U3D_QISAR1 is read update */ |
| 479 | qmu_status = mtu3_readl(mbase, U3D_QISAR1); |
| 480 | qmu_status &= mtu3_readl(mbase, U3D_QIER1); |
| 481 | |
| 482 | qmu_done_status = mtu3_readl(mbase, U3D_QISAR0); |
| 483 | qmu_done_status &= mtu3_readl(mbase, U3D_QIER0); |
| 484 | mtu3_writel(mbase, U3D_QISAR0, qmu_done_status); /* W1C */ |
| 485 | dev_dbg(mtu->dev, "=== QMUdone[tx=%x, rx=%x] QMUexp[%x] ===\n", |
| 486 | (qmu_done_status & 0xFFFF), qmu_done_status >> 16, |
| 487 | qmu_status); |
| 488 | |
| 489 | if (qmu_done_status) |
| 490 | qmu_done_isr(mtu, qmu_done_status); |
| 491 | |
| 492 | if (qmu_status) |
| 493 | qmu_exception_isr(mtu, qmu_status); |
| 494 | |
| 495 | return IRQ_HANDLED; |
| 496 | } |
| 497 | |
| 498 | void mtu3_qmu_init(struct mtu3 *mtu) |
| 499 | { |
| 500 | compiletime_assert(QMU_GPD_SIZE == 16, "QMU_GPD size SHOULD be 16B"); |
| 501 | } |
| 502 | |
| 503 | void mtu3_qmu_exit(struct mtu3 *mtu) |
| 504 | { |
| 505 | } |