| Icenowy Zheng | 13d7170 | 2022-08-25 16:11:18 +0800 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ |
| Green Wan | 06a3e40 | 2021-05-27 06:52:11 -0700 | [diff] [blame] | 2 | /* |
| Icenowy Zheng | 13d7170 | 2022-08-25 16:11:18 +0800 | [diff] [blame^] | 3 | * Copyright (C) 2019 SiFive, Inc. |
| Green Wan | 06a3e40 | 2021-05-27 06:52:11 -0700 | [diff] [blame] | 4 | * Wesley Terpstra |
| 5 | * Paul Walmsley |
| 6 | * Zong Li |
| Green Wan | 06a3e40 | 2021-05-27 06:52:11 -0700 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H |
| 10 | #define __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H |
| 11 | |
| 12 | /* Clock indexes for use by Device Tree data and the PRCI driver */ |
| 13 | |
| Icenowy Zheng | 13d7170 | 2022-08-25 16:11:18 +0800 | [diff] [blame^] | 14 | #define FU740_PRCI_CLK_COREPLL 0 |
| 15 | #define FU740_PRCI_CLK_DDRPLL 1 |
| 16 | #define FU740_PRCI_CLK_GEMGXLPLL 2 |
| 17 | #define FU740_PRCI_CLK_DVFSCOREPLL 3 |
| 18 | #define FU740_PRCI_CLK_HFPCLKPLL 4 |
| 19 | #define FU740_PRCI_CLK_CLTXPLL 5 |
| 20 | #define FU740_PRCI_CLK_TLCLK 6 |
| 21 | #define FU740_PRCI_CLK_PCLK 7 |
| 22 | #define FU740_PRCI_CLK_PCIE_AUX 8 |
| Green Wan | 06a3e40 | 2021-05-27 06:52:11 -0700 | [diff] [blame] | 23 | |
| Icenowy Zheng | 13d7170 | 2022-08-25 16:11:18 +0800 | [diff] [blame^] | 24 | #endif /* __DT_BINDINGS_CLOCK_SIFIVE_FU740_PRCI_H */ |