Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * |
| 3 | * Common functions for OMAP4 based boards |
| 4 | * |
| 5 | * (C) Copyright 2010 |
| 6 | * Texas Instruments, <www.ti.com> |
| 7 | * |
| 8 | * Author : |
| 9 | * Aneesh V <aneesh@ti.com> |
| 10 | * Steve Sakoman <steve@sakoman.com> |
| 11 | * |
| 12 | * See file CREDITS for list of people who contributed to this |
| 13 | * project. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License as |
| 17 | * published by the Free Software Foundation; either version 2 of |
| 18 | * the License, or (at your option) any later version. |
| 19 | * |
| 20 | * This program is distributed in the hope that it will be useful, |
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 23 | * GNU General Public License for more details. |
| 24 | * |
| 25 | * You should have received a copy of the GNU General Public License |
| 26 | * along with this program; if not, write to the Free Software |
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 28 | * MA 02111-1307 USA |
| 29 | */ |
| 30 | #include <common.h> |
Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 31 | #include <asm/armv7.h> |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 32 | #include <asm/arch/cpu.h> |
| 33 | #include <asm/arch/sys_proto.h> |
Aneesh V | 04bd2b9 | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 34 | #include <asm/sizes.h> |
Aneesh V | c0e8852 | 2011-07-21 09:10:12 -0400 | [diff] [blame] | 35 | #include <asm/arch/emif.h> |
Aneesh V | f908b63 | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 36 | #include "omap4_mux_data.h" |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 37 | |
Nishanth Menon | 4e5dd66 | 2010-11-19 11:19:40 -0500 | [diff] [blame] | 38 | DECLARE_GLOBAL_DATA_PTR; |
| 39 | |
Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 40 | u32 *const omap4_revision = (u32 *)OMAP4_SRAM_SCRATCH_OMAP4_REV; |
| 41 | |
Aneesh V | 13a74c1 | 2011-07-21 09:10:27 -0400 | [diff] [blame^] | 42 | #ifdef CONFIG_SPL_BUILD |
| 43 | /* |
| 44 | * We use static variables because global data is not ready yet. |
| 45 | * Initialized data is available in SPL right from the beginning. |
| 46 | * We would not typically need to save these parameters in regular |
| 47 | * U-Boot. This is needed only in SPL at the moment. |
| 48 | */ |
| 49 | u32 omap4_boot_device = BOOT_DEVICE_MMC1; |
| 50 | u32 omap4_boot_mode = MMCSD_MODE_FAT; |
| 51 | |
| 52 | u32 omap_boot_device(void) |
| 53 | { |
| 54 | return omap4_boot_device; |
| 55 | } |
| 56 | |
| 57 | u32 omap_boot_mode(void) |
| 58 | { |
| 59 | return omap4_boot_mode; |
| 60 | } |
| 61 | #endif |
| 62 | |
Aneesh V | f908b63 | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 63 | void do_set_mux(u32 base, struct pad_conf_entry const *array, int size) |
| 64 | { |
| 65 | int i; |
| 66 | struct pad_conf_entry *pad = (struct pad_conf_entry *) array; |
| 67 | |
| 68 | for (i = 0; i < size; i++, pad++) |
| 69 | writew(pad->val, base + pad->offset); |
| 70 | } |
| 71 | |
| 72 | static void set_muxconf_regs_essential(void) |
| 73 | { |
| 74 | do_set_mux(CONTROL_PADCONF_CORE, core_padconf_array_essential, |
| 75 | sizeof(core_padconf_array_essential) / |
| 76 | sizeof(struct pad_conf_entry)); |
| 77 | |
| 78 | do_set_mux(CONTROL_PADCONF_WKUP, wkup_padconf_array_essential, |
| 79 | sizeof(wkup_padconf_array_essential) / |
| 80 | sizeof(struct pad_conf_entry)); |
| 81 | } |
| 82 | |
| 83 | static void set_mux_conf_regs(void) |
| 84 | { |
| 85 | switch (omap4_hw_init_context()) { |
| 86 | case OMAP_INIT_CONTEXT_SPL: |
| 87 | set_muxconf_regs_essential(); |
| 88 | break; |
| 89 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL: |
| 90 | set_muxconf_regs_non_essential(); |
| 91 | break; |
| 92 | case OMAP_INIT_CONTEXT_UBOOT_FROM_NOR: |
| 93 | case OMAP_INIT_CONTEXT_UBOOT_AFTER_CH: |
| 94 | set_muxconf_regs_essential(); |
| 95 | set_muxconf_regs_non_essential(); |
| 96 | break; |
| 97 | } |
| 98 | } |
| 99 | |
Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 100 | static u32 cortex_a9_rev(void) |
| 101 | { |
| 102 | |
| 103 | unsigned int rev; |
| 104 | |
| 105 | /* Read Main ID Register (MIDR) */ |
| 106 | asm ("mrc p15, 0, %0, c0, c0, 0" : "=r" (rev)); |
| 107 | |
| 108 | return rev; |
| 109 | } |
| 110 | |
| 111 | static void init_omap4_revision(void) |
| 112 | { |
| 113 | /* |
| 114 | * For some of the ES2/ES1 boards ID_CODE is not reliable: |
| 115 | * Also, ES1 and ES2 have different ARM revisions |
| 116 | * So use ARM revision for identification |
| 117 | */ |
| 118 | unsigned int arm_rev = cortex_a9_rev(); |
| 119 | |
| 120 | switch (arm_rev) { |
| 121 | case MIDR_CORTEX_A9_R0P1: |
| 122 | *omap4_revision = OMAP4430_ES1_0; |
| 123 | break; |
| 124 | case MIDR_CORTEX_A9_R1P2: |
| 125 | switch (readl(CONTROL_ID_CODE)) { |
| 126 | case OMAP4_CONTROL_ID_CODE_ES2_0: |
| 127 | *omap4_revision = OMAP4430_ES2_0; |
| 128 | break; |
| 129 | case OMAP4_CONTROL_ID_CODE_ES2_1: |
| 130 | *omap4_revision = OMAP4430_ES2_1; |
| 131 | break; |
| 132 | case OMAP4_CONTROL_ID_CODE_ES2_2: |
| 133 | *omap4_revision = OMAP4430_ES2_2; |
| 134 | break; |
| 135 | default: |
| 136 | *omap4_revision = OMAP4430_ES2_0; |
| 137 | break; |
| 138 | } |
| 139 | break; |
| 140 | case MIDR_CORTEX_A9_R1P3: |
| 141 | *omap4_revision = OMAP4430_ES2_3; |
| 142 | break; |
| 143 | default: |
| 144 | *omap4_revision = OMAP4430_SILICON_ID_INVALID; |
| 145 | break; |
| 146 | } |
| 147 | } |
| 148 | |
| 149 | void omap_rev_string(char *omap4_rev_string) |
| 150 | { |
| 151 | u32 omap4_rev = omap_revision(); |
| 152 | u32 omap4_variant = (omap4_rev & 0xFFFF0000) >> 16; |
| 153 | u32 major_rev = (omap4_rev & 0x00000F00) >> 8; |
| 154 | u32 minor_rev = (omap4_rev & 0x000000F0) >> 4; |
| 155 | |
| 156 | sprintf(omap4_rev_string, "OMAP%x ES%x.%x", omap4_variant, major_rev, |
| 157 | minor_rev); |
| 158 | } |
| 159 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 160 | /* |
| 161 | * Routine: s_init |
Aneesh V | f908b63 | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 162 | * Description: Does early system init of watchdog, muxing, andclocks |
| 163 | * Watchdog disable is done always. For the rest what gets done |
| 164 | * depends on the boot mode in which this function is executed |
| 165 | * 1. s_init of SPL running from SRAM |
| 166 | * 2. s_init of U-Boot running from FLASH |
| 167 | * 3. s_init of U-Boot loaded to SDRAM by SPL |
| 168 | * 4. s_init of U-Boot loaded to SDRAM by ROM code using the |
| 169 | * Configuration Header feature |
| 170 | * Please have a look at the respective functions to see what gets |
| 171 | * done in each of these cases |
| 172 | * This function is called with SRAM stack. |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 173 | */ |
| 174 | void s_init(void) |
| 175 | { |
Aneesh V | 162ced3 | 2011-07-21 09:10:04 -0400 | [diff] [blame] | 176 | init_omap4_revision(); |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 177 | watchdog_init(); |
Aneesh V | f908b63 | 2011-07-21 09:10:01 -0400 | [diff] [blame] | 178 | set_mux_conf_regs(); |
Aneesh V | b8e60b9 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 179 | #ifdef CONFIG_SPL_BUILD |
| 180 | preloader_console_init(); |
| 181 | #endif |
Aneesh V | 0d2628b | 2011-07-21 09:10:07 -0400 | [diff] [blame] | 182 | prcm_init(); |
Aneesh V | b8e60b9 | 2011-07-21 09:10:21 -0400 | [diff] [blame] | 183 | #ifdef CONFIG_SPL_BUILD |
| 184 | /* For regular u-boot sdram_init() is called from dram_init() */ |
| 185 | sdram_init(); |
| 186 | #endif |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 187 | } |
| 188 | |
| 189 | /* |
| 190 | * Routine: wait_for_command_complete |
| 191 | * Description: Wait for posting to finish on watchdog |
| 192 | */ |
| 193 | void wait_for_command_complete(struct watchdog *wd_base) |
| 194 | { |
| 195 | int pending = 1; |
| 196 | do { |
| 197 | pending = readl(&wd_base->wwps); |
| 198 | } while (pending); |
| 199 | } |
| 200 | |
| 201 | /* |
| 202 | * Routine: watchdog_init |
| 203 | * Description: Shut down watch dogs |
| 204 | */ |
| 205 | void watchdog_init(void) |
| 206 | { |
| 207 | struct watchdog *wd2_base = (struct watchdog *)WDT2_BASE; |
| 208 | |
| 209 | writel(WD_UNLOCK1, &wd2_base->wspr); |
| 210 | wait_for_command_complete(wd2_base); |
| 211 | writel(WD_UNLOCK2, &wd2_base->wspr); |
| 212 | } |
| 213 | |
Aneesh V | 04bd2b9 | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 214 | |
| 215 | /* |
| 216 | * This function finds the SDRAM size available in the system |
| 217 | * based on DMM section configurations |
| 218 | * This is needed because the size of memory installed may be |
| 219 | * different on different versions of the board |
| 220 | */ |
Aneesh V | cc56558 | 2011-07-21 09:10:09 -0400 | [diff] [blame] | 221 | u32 omap4_sdram_size(void) |
Aneesh V | 04bd2b9 | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 222 | { |
| 223 | u32 section, i, total_size = 0, size, addr; |
| 224 | for (i = 0; i < 4; i++) { |
Aneesh V | c0e8852 | 2011-07-21 09:10:12 -0400 | [diff] [blame] | 225 | section = __raw_readl(OMAP44XX_DMM_LISA_MAP_BASE + i*4); |
| 226 | addr = section & OMAP44XX_SYS_ADDR_MASK; |
Aneesh V | 04bd2b9 | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 227 | /* See if the address is valid */ |
| 228 | if ((addr >= OMAP44XX_DRAM_ADDR_SPACE_START) && |
| 229 | (addr < OMAP44XX_DRAM_ADDR_SPACE_END)) { |
Aneesh V | c0e8852 | 2011-07-21 09:10:12 -0400 | [diff] [blame] | 230 | size = ((section & OMAP44XX_SYS_SIZE_MASK) >> |
| 231 | OMAP44XX_SYS_SIZE_SHIFT); |
Aneesh V | 04bd2b9 | 2010-09-12 10:32:55 +0530 | [diff] [blame] | 232 | size = 1 << size; |
| 233 | size *= SZ_16M; |
| 234 | total_size += size; |
| 235 | } |
| 236 | } |
| 237 | return total_size; |
| 238 | } |
| 239 | |
| 240 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 241 | /* |
| 242 | * Routine: dram_init |
| 243 | * Description: sets uboots idea of sdram size |
| 244 | */ |
| 245 | int dram_init(void) |
| 246 | { |
Aneesh V | cc56558 | 2011-07-21 09:10:09 -0400 | [diff] [blame] | 247 | sdram_init(); |
| 248 | gd->ram_size = omap4_sdram_size(); |
Steve Sakoman | 97c57f1 | 2010-09-29 20:59:51 -0700 | [diff] [blame] | 249 | |
Steve Sakoman | 1ad2158 | 2010-06-08 13:07:46 -0700 | [diff] [blame] | 250 | return 0; |
| 251 | } |
| 252 | |
| 253 | /* |
| 254 | * Print board information |
| 255 | */ |
| 256 | int checkboard(void) |
| 257 | { |
| 258 | puts(sysinfo.board_string); |
| 259 | return 0; |
| 260 | } |
| 261 | |
Steve Sakoman | 9bb65b5 | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 262 | /* |
| 263 | * This function is called by start_armboot. You can reliably use static |
| 264 | * data. Any boot-time function that require static data should be |
| 265 | * called from here |
| 266 | */ |
| 267 | int arch_cpu_init(void) |
| 268 | { |
Steve Sakoman | 9bb65b5 | 2010-07-15 13:43:10 -0700 | [diff] [blame] | 269 | return 0; |
| 270 | } |
Aneesh V | e3405bd | 2011-06-16 23:30:52 +0000 | [diff] [blame] | 271 | |
| 272 | #ifndef CONFIG_SYS_L2CACHE_OFF |
| 273 | void v7_outer_cache_enable(void) |
| 274 | { |
| 275 | set_pl310_ctrl_reg(1); |
| 276 | } |
| 277 | |
| 278 | void v7_outer_cache_disable(void) |
| 279 | { |
| 280 | set_pl310_ctrl_reg(0); |
| 281 | } |
| 282 | #endif |