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Bin Meng00ffb4d2015-02-02 22:35:23 +08001/*
2 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7#ifndef _QUARK_DEVICE_H_
8#define _QUARK_DEVICE_H_
9
Bin Meng5efb4152016-05-25 19:19:09 -070010/*
11 * Internal PCI device numbers within the SoC.
12 *
13 * Note it must start with 0x_ prefix, as the device number macro will be
14 * included in the ACPI ASL files (see irq_helper.h and irq_route.h).
15 */
Bin Meng00ffb4d2015-02-02 22:35:23 +080016
Bin Meng5efb4152016-05-25 19:19:09 -070017#define QUARK_HOST_BRIDGE_DEV 0x00
Bin Mengef9e9f92015-05-25 22:35:06 +080018#define QUARK_HOST_BRIDGE_FUNC 0
19
Bin Meng5efb4152016-05-25 19:19:09 -070020#define QUARK_DEV_20 0x14
Bin Mengef9e9f92015-05-25 22:35:06 +080021#define QUARK_MMC_SDIO_FUNC 0
22#define QUARK_UART0_FUNC 1
23#define QUARK_USB_DEVICE_FUNC 2
24#define QUARK_USB_EHCI_FUNC 3
25#define QUARK_USB_OHCI_FUNC 4
26#define QUARK_UART1_FUNC 5
27#define QUARK_EMAC0_FUNC 6
28#define QUARK_EMAC1_FUNC 7
29
Bin Meng5efb4152016-05-25 19:19:09 -070030#define QUARK_DEV_21 0x15
Bin Mengef9e9f92015-05-25 22:35:06 +080031#define QUARK_SPI0_FUNC 0
32#define QUARK_SPI1_FUNC 1
33#define QUARK_I2C_GPIO_FUNC 2
34
Bin Meng5efb4152016-05-25 19:19:09 -070035#define QUARK_DEV_23 0x17
Bin Mengef9e9f92015-05-25 22:35:06 +080036#define QUARK_PCIE0_FUNC 0
37#define QUARK_PCIE1_FUNC 1
38
Bin Meng5efb4152016-05-25 19:19:09 -070039#define QUARK_LGC_BRIDGE_DEV 0x1f
Bin Mengef9e9f92015-05-25 22:35:06 +080040#define QUARK_LGC_BRIDGE_FUNC 0
41
Bin Meng5efb4152016-05-25 19:19:09 -070042#ifndef __ASSEMBLY__
43#include <pci.h>
44
Bin Mengef9e9f92015-05-25 22:35:06 +080045#define QUARK_HOST_BRIDGE \
46 PCI_BDF(0, QUARK_HOST_BRIDGE_DEV, QUARK_HOST_BRIDGE_FUNC)
47#define QUARK_MMC_SDIO \
48 PCI_BDF(0, QUARK_DEV_20, QUARK_MMC_SDIO_FUNC)
49#define QUARK_UART0 \
50 PCI_BDF(0, QUARK_DEV_20, QUARK_UART0_FUNC)
51#define QUARK_USB_DEVICE \
52 PCI_BDF(0, QUARK_DEV_20, QUARK_USB_DEVICE_FUNC)
53#define QUARK_USB_EHCI \
54 PCI_BDF(0, QUARK_DEV_20, QUARK_USB_EHCI_FUNC)
55#define QUARK_USB_OHCI \
56 PCI_BDF(0, QUARK_DEV_20, QUARK_USB_OHCI_FUNC)
57#define QUARK_UART1 \
58 PCI_BDF(0, QUARK_DEV_20, QUARK_UART1_FUNC)
59#define QUARK_EMAC0 \
60 PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC0_FUNC)
61#define QUARK_EMAC1 \
62 PCI_BDF(0, QUARK_DEV_20, QUARK_EMAC1_FUNC)
63#define QUARK_SPI0 \
64 PCI_BDF(0, QUARK_DEV_21, QUARK_SPI0_FUNC)
65#define QUARK_SPI1 \
66 PCI_BDF(0, QUARK_DEV_21, QUARK_SPI1_FUNC)
67#define QUARK_I2C_GPIO \
68 PCI_BDF(0, QUARK_DEV_21, QUARK_I2C_GPIO_FUNC)
69#define QUARK_PCIE0 \
70 PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE0_FUNC)
71#define QUARK_PCIE1 \
72 PCI_BDF(0, QUARK_DEV_23, QUARK_PCIE1_FUNC)
73#define QUARK_LEGACY_BRIDGE \
74 PCI_BDF(0, QUARK_LGC_BRIDGE_DEV, QUARK_LGC_BRIDGE_FUNC)
Bin Meng5efb4152016-05-25 19:19:09 -070075#endif /* __ASSEMBLY__ */
Bin Meng00ffb4d2015-02-02 22:35:23 +080076
77#endif /* _QUARK_DEVICE_H_ */