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git01.mediatek.com / filogic / uboot / 13a489e91d44ba1cb82776277517629920270128 / . / arch / arm / cpu / tegra114-common / pinmux.c
blob: 4983a05090a2dad037318a42ecec4c6014f54da6 [file] [log] [blame]
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]1/*
2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16
17/* Tegra114 pin multiplexing functions */
18
19#include <common.h>
20#include <asm/io.h>
21#include <asm/arch/tegra.h>
22#include <asm/arch/pinmux.h>
23
24struct tegra_pingroup_desc {
25 const char *name;
26 enum pmux_func funcs[4];
27 enum pmux_func func_safe;
28 enum pmux_vddio vddio;
29 enum pmux_pin_io io;
30};
31
32#define PMUX_MUXCTL_SHIFT 0
33#define PMUX_PULL_SHIFT 2
34#define PMUX_TRISTATE_SHIFT 4
35#define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
36#define PMUX_IO_SHIFT 5
37#define PMUX_OD_SHIFT 6
38#define PMUX_LOCK_SHIFT 7
39#define PMUX_IO_RESET_SHIFT 8
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]40#define PMUX_RCV_SEL_SHIFT 9
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]41
Tom Warrene6194612013-03-11 16:43:49 -0700[diff] [blame]42#define PGRP_HSM_SHIFT 2
43#define PGRP_SCHMT_SHIFT 3
44#define PGRP_LPMD_SHIFT 4
45#define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
46#define PGRP_DRVDN_SHIFT 12
47#define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
48#define PGRP_DRVUP_SHIFT 20
49#define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
50#define PGRP_SLWR_SHIFT 28
51#define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
52#define PGRP_SLWF_SHIFT 30
53#define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
54
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]55/* Convenient macro for defining pin group properties */
56#define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
57 { \
58 .vddio = PMUX_VDDIO_ ## vdd, \
59 .funcs = { \
60 PMUX_FUNC_ ## f0, \
61 PMUX_FUNC_ ## f1, \
62 PMUX_FUNC_ ## f2, \
63 PMUX_FUNC_ ## f3, \
64 }, \
65 .func_safe = PMUX_FUNC_RSVD1, \
66 .io = PMUX_PIN_ ## iod, \
67 }
68
69/* Input and output pins */
70#define PINI(pg_name, vdd, f0, f1, f2, f3) \
71 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
72#define PINO(pg_name, vdd, f0, f1, f2, f3) \
73 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
74
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]75/* A pin group number which is not used */
76#define PIN_RESERVED \
77 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
78
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]79const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
80 /* NAME VDD f0 f1 f2 f3 */
81 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
82 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
83 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
84 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
85 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
86 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
87 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
88 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
89 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
90 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
91 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
92 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
93 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
94 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
95 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
96 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
97 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
98 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
99 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
100 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
101 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
102 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
103 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
104 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]105 PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
106 PIN_RESERVED,
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]107 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
108 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]109 PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
110 PIN_RESERVED,
111 PIN_RESERVED,
112 PIN_RESERVED,
113 PIN_RESERVED,
114 PIN_RESERVED,
115 PIN_RESERVED,
116 PIN_RESERVED,
117 PIN_RESERVED,
118 PIN_RESERVED,
119 PIN_RESERVED,
120 PIN_RESERVED,
121 PIN_RESERVED,
122 PIN_RESERVED,
123 PIN_RESERVED,
124 PIN_RESERVED,
125 PIN_RESERVED,
126 PIN_RESERVED,
127 PIN_RESERVED,
128 PIN_RESERVED,
129 PIN_RESERVED,
130 PIN_RESERVED,
131 PIN_RESERVED,
132 PIN_RESERVED,
133 PIN_RESERVED,
134 PIN_RESERVED,
135 PIN_RESERVED,
136 PIN_RESERVED,
137 PIN_RESERVED,
138 PIN_RESERVED,
139 PIN_RESERVED,
140 PIN_RESERVED,
141 PIN_RESERVED,
142 PIN_RESERVED,
143 PIN_RESERVED,
144 PIN_RESERVED,
145 PIN_RESERVED,
146 PIN_RESERVED,
147 PIN_RESERVED,
148 PIN_RESERVED,
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]149 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
150 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
151 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]152 PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
153 PIN_RESERVED,
154 PIN_RESERVED,
155 PIN_RESERVED,
156 PIN_RESERVED,
157 PIN_RESERVED,
158 PIN_RESERVED,
159 PIN_RESERVED,
160 PIN_RESERVED,
161 PIN_RESERVED,
162 PIN_RESERVED,
163 PIN_RESERVED,
164 PIN_RESERVED,
165 PIN_RESERVED,
166 PIN_RESERVED,
167 PIN_RESERVED,
168 PIN_RESERVED,
169 PIN_RESERVED,
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]170 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
171 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
172 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
173 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
174 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
175 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
176 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
177 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
178 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
179 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
180 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
181 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
182 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
183 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
184 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
185 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
186 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
187 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
188 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
189 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
190 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
191 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
192 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
193 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
194 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
195 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
196 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
197 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
198 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
199 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
200 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
201 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
202 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
203 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
204 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
205 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
206 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
207 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
208 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
209 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
210 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
211 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
212 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
213 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
214 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
215 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
216 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
217 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
218 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
219 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
220 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
221 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
222 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
223 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
224 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
225 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
226 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
227 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
228 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
229 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
230 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
231 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
232 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
233 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
234 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
235 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
236 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
237 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
238 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
239 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
240 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]241 PIN_RESERVED, /* Reserved by t114: 0x3280 */
Tom Warren326127f2013-03-13 15:00:54 -0700[diff] [blame]242 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]243 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
244 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
245 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
246 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
247 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
248 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
249 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
250 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
251 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
252 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
253 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
254 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
255 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
256 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
257 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
258 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
259 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
260 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
261 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
262 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
263 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
264 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
265 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
266 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]267 PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
268 PIN_RESERVED,
269 PIN_RESERVED,
270 PIN_RESERVED,
271 PIN_RESERVED,
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]272 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
273 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
274 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
275 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
276 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
277 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
278 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
279 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
280 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
281 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
282 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
283 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
284 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
285 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
286 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
287 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
288 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
289 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
290 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
291 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
292 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
293 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
294 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
295 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
296 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
297 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
298 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]299 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
300 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
301 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
302 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
303 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
304 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
305 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
306 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
307 PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
308 PIN_RESERVED,
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]309 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
310 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
311 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
312 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
313 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
314 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]315 PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
316 PIN_RESERVED,
317 PIN_RESERVED,
318 PIN_RESERVED,
319 PIN_RESERVED,
320 PIN_RESERVED,
321 PIN_RESERVED,
322 PIN_RESERVED,
323 PIN_RESERVED,
324 PIN_RESERVED,
325 PIN_RESERVED,
326 PIN_RESERVED,
327 PIN_RESERVED,
328 PIN_RESERVED,
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]329 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
330 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]331 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
332 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
333 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
334 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
335 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]336 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]337 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
338 PIN_RESERVED, /* Reserved by t114: 0x3404 */
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]339 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
340};
341
342void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
343{
344 struct pmux_tri_ctlr *pmt =
345 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
346 u32 *tri = &pmt->pmt_ctl[pin];
347 u32 reg;
348
349 /* Error check on pin */
350 assert(pmux_pingrp_isvalid(pin));
351
352 reg = readl(tri);
353 if (enable)
354 reg |= PMUX_TRISTATE_MASK;
355 else
356 reg &= ~PMUX_TRISTATE_MASK;
357 writel(reg, tri);
358}
359
360void pinmux_tristate_enable(enum pmux_pingrp pin)
361{
362 pinmux_set_tristate(pin, 1);
363}
364
365void pinmux_tristate_disable(enum pmux_pingrp pin)
366{
367 pinmux_set_tristate(pin, 0);
368}
369
370void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
371{
372 struct pmux_tri_ctlr *pmt =
373 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
374 u32 *pull = &pmt->pmt_ctl[pin];
375 u32 reg;
376
377 /* Error check on pin and pupd */
378 assert(pmux_pingrp_isvalid(pin));
379 assert(pmux_pin_pupd_isvalid(pupd));
380
381 reg = readl(pull);
382 reg &= ~(0x3 << PMUX_PULL_SHIFT);
383 reg |= (pupd << PMUX_PULL_SHIFT);
384 writel(reg, pull);
385}
386
387void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
388{
389 struct pmux_tri_ctlr *pmt =
390 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
391 u32 *muxctl = &pmt->pmt_ctl[pin];
392 int i, mux = -1;
393 u32 reg;
394
395 /* Error check on pin and func */
396 assert(pmux_pingrp_isvalid(pin));
397 assert(pmux_func_isvalid(func));
398
399 /* Handle special values */
400 if (func == PMUX_FUNC_SAFE)
401 func = tegra_soc_pingroups[pin].func_safe;
402
403 if (func & PMUX_FUNC_RSVD1) {
404 mux = func & 0x3;
405 } else {
406 /* Search for the appropriate function */
407 for (i = 0; i < 4; i++) {
408 if (tegra_soc_pingroups[pin].funcs[i] == func) {
409 mux = i;
410 break;
411 }
412 }
413 }
414 assert(mux != -1);
415
416 reg = readl(muxctl);
417 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
418 reg |= (mux << PMUX_MUXCTL_SHIFT);
419 writel(reg, muxctl);
420
421}
422
423void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
424{
425 struct pmux_tri_ctlr *pmt =
426 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
427 u32 *pin_io = &pmt->pmt_ctl[pin];
428 u32 reg;
429
430 /* Error check on pin and io */
431 assert(pmux_pingrp_isvalid(pin));
432 assert(pmux_pin_io_isvalid(io));
433
434 reg = readl(pin_io);
435 reg &= ~(0x1 << PMUX_IO_SHIFT);
436 reg |= (io & 0x1) << PMUX_IO_SHIFT;
437 writel(reg, pin_io);
438}
439
440static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
441{
442 struct pmux_tri_ctlr *pmt =
443 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
444 u32 *pin_lock = &pmt->pmt_ctl[pin];
445 u32 reg;
446
447 /* Error check on pin and lock */
448 assert(pmux_pingrp_isvalid(pin));
449 assert(pmux_pin_lock_isvalid(lock));
450
451 if (lock == PMUX_PIN_LOCK_DEFAULT)
452 return 0;
453
454 reg = readl(pin_lock);
455 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
456 if (lock == PMUX_PIN_LOCK_ENABLE)
457 reg |= (0x1 << PMUX_LOCK_SHIFT);
458 else {
459 /* lock == DISABLE, which isn't possible */
460 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
461 __func__, lock);
462 }
463 writel(reg, pin_lock);
464
465 return 0;
466}
467
468static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
469{
470 struct pmux_tri_ctlr *pmt =
471 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
472 u32 *pin_od = &pmt->pmt_ctl[pin];
473 u32 reg;
474
475 /* Error check on pin and od */
476 assert(pmux_pingrp_isvalid(pin));
477 assert(pmux_pin_od_isvalid(od));
478
479 if (od == PMUX_PIN_OD_DEFAULT)
480 return 0;
481
482 reg = readl(pin_od);
483 reg &= ~(0x1 << PMUX_OD_SHIFT);
484 if (od == PMUX_PIN_OD_ENABLE)
485 reg |= (0x1 << PMUX_OD_SHIFT);
486 writel(reg, pin_od);
487
488 return 0;
489}
490
491static int pinmux_set_ioreset(enum pmux_pingrp pin,
492 enum pmux_pin_ioreset ioreset)
493{
494 struct pmux_tri_ctlr *pmt =
495 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
496 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
497 u32 reg;
498
499 /* Error check on pin and ioreset */
500 assert(pmux_pingrp_isvalid(pin));
501 assert(pmux_pin_ioreset_isvalid(ioreset));
502
503 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
504 return 0;
505
506 reg = readl(pin_ioreset);
507 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
508 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
509 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
510 writel(reg, pin_ioreset);
511
512 return 0;
513}
514
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]515static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
516 enum pmux_pin_rcv_sel rcv_sel)
517{
518 struct pmux_tri_ctlr *pmt =
519 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
520 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
521 u32 reg;
522
523 /* Error check on pin and rcv_sel */
524 assert(pmux_pingrp_isvalid(pin));
525 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
526
527 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
528 return 0;
529
530 reg = readl(pin_rcv_sel);
531 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
532 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
533 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
534 writel(reg, pin_rcv_sel);
535
536 return 0;
537}
538
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]539void pinmux_config_pingroup(struct pingroup_config *config)
540{
541 enum pmux_pingrp pin = config->pingroup;
542
543 pinmux_set_func(pin, config->func);
544 pinmux_set_pullupdown(pin, config->pull);
545 pinmux_set_tristate(pin, config->tristate);
546 pinmux_set_io(pin, config->io);
547 pinmux_set_lock(pin, config->lock);
548 pinmux_set_od(pin, config->od);
549 pinmux_set_ioreset(pin, config->ioreset);
Tom Warren8495b222013-03-01 14:38:20 -0700[diff] [blame]550 pinmux_set_rcv_sel(pin, config->rcv_sel);
Tom Warrene3d95bc2013-01-28 13:32:10 +0000[diff] [blame]551}
552
553void pinmux_config_table(struct pingroup_config *config, int len)
554{
555 int i;
556
557 for (i = 0; i < len; i++)
558 pinmux_config_pingroup(&config[i]);
559}
Tom Warrene6194612013-03-11 16:43:49 -0700[diff] [blame]560
561static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
562{
563 struct pmux_tri_ctlr *pmt =
564 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
565 u32 *pad_slwf = &pmt->pmt_drive[pad];
566 u32 reg;
567
568 /* Error check on pad and slwf */
569 assert(pmux_padgrp_isvalid(pad));
570 assert(pmux_pad_slw_isvalid(slwf));
571
572 /* NONE means unspecified/do not change/use POR value */
573 if (slwf == PGRP_SLWF_NONE)
574 return 0;
575
576 reg = readl(pad_slwf);
577 reg &= ~PGRP_SLWF_MASK;
578 reg |= (slwf << PGRP_SLWF_SHIFT);
579 writel(reg, pad_slwf);
580
581 return 0;
582}
583
584static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
585{
586 struct pmux_tri_ctlr *pmt =
587 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
588 u32 *pad_slwr = &pmt->pmt_drive[pad];
589 u32 reg;
590
591 /* Error check on pad and slwr */
592 assert(pmux_padgrp_isvalid(pad));
593 assert(pmux_pad_slw_isvalid(slwr));
594
595 /* NONE means unspecified/do not change/use POR value */
596 if (slwr == PGRP_SLWR_NONE)
597 return 0;
598
599 reg = readl(pad_slwr);
600 reg &= ~PGRP_SLWR_MASK;
601 reg |= (slwr << PGRP_SLWR_SHIFT);
602 writel(reg, pad_slwr);
603
604 return 0;
605}
606
607static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
608{
609 struct pmux_tri_ctlr *pmt =
610 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
611 u32 *pad_drvup = &pmt->pmt_drive[pad];
612 u32 reg;
613
614 /* Error check on pad and drvup */
615 assert(pmux_padgrp_isvalid(pad));
616 assert(pmux_pad_drv_isvalid(drvup));
617
618 /* NONE means unspecified/do not change/use POR value */
619 if (drvup == PGRP_DRVUP_NONE)
620 return 0;
621
622 reg = readl(pad_drvup);
623 reg &= ~PGRP_DRVUP_MASK;
624 reg |= (drvup << PGRP_DRVUP_SHIFT);
625 writel(reg, pad_drvup);
626
627 return 0;
628}
629
630static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
631{
632 struct pmux_tri_ctlr *pmt =
633 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
634 u32 *pad_drvdn = &pmt->pmt_drive[pad];
635 u32 reg;
636
637 /* Error check on pad and drvdn */
638 assert(pmux_padgrp_isvalid(pad));
639 assert(pmux_pad_drv_isvalid(drvdn));
640
641 /* NONE means unspecified/do not change/use POR value */
642 if (drvdn == PGRP_DRVDN_NONE)
643 return 0;
644
645 reg = readl(pad_drvdn);
646 reg &= ~PGRP_DRVDN_MASK;
647 reg |= (drvdn << PGRP_DRVDN_SHIFT);
648 writel(reg, pad_drvdn);
649
650 return 0;
651}
652
653static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
654{
655 struct pmux_tri_ctlr *pmt =
656 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
657 u32 *pad_lpmd = &pmt->pmt_drive[pad];
658 u32 reg;
659
660 /* Error check pad and lpmd value */
661 assert(pmux_padgrp_isvalid(pad));
662 assert(pmux_pad_lpmd_isvalid(lpmd));
663
664 /* NONE means unspecified/do not change/use POR value */
665 if (lpmd == PGRP_LPMD_NONE)
666 return 0;
667
668 reg = readl(pad_lpmd);
669 reg &= ~PGRP_LPMD_MASK;
670 reg |= (lpmd << PGRP_LPMD_SHIFT);
671 writel(reg, pad_lpmd);
672
673 return 0;
674}
675
676static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
677{
678 struct pmux_tri_ctlr *pmt =
679 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
680 u32 *pad_schmt = &pmt->pmt_drive[pad];
681 u32 reg;
682
683 /* Error check pad */
684 assert(pmux_padgrp_isvalid(pad));
685
686 /* NONE means unspecified/do not change/use POR value */
687 if (schmt == PGRP_SCHMT_NONE)
688 return 0;
689
690 reg = readl(pad_schmt);
691 reg &= ~(1 << PGRP_SCHMT_SHIFT);
692 if (schmt == PGRP_SCHMT_ENABLE)
693 reg |= (0x1 << PGRP_SCHMT_SHIFT);
694 writel(reg, pad_schmt);
695
696 return 0;
697}
698static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
699{
700 struct pmux_tri_ctlr *pmt =
701 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
702 u32 *pad_hsm = &pmt->pmt_drive[pad];
703 u32 reg;
704
705 /* Error check pad */
706 assert(pmux_padgrp_isvalid(pad));
707
708 /* NONE means unspecified/do not change/use POR value */
709 if (hsm == PGRP_HSM_NONE)
710 return 0;
711
712 reg = readl(pad_hsm);
713 reg &= ~(1 << PGRP_HSM_SHIFT);
714 if (hsm == PGRP_HSM_ENABLE)
715 reg |= (0x1 << PGRP_HSM_SHIFT);
716 writel(reg, pad_hsm);
717
718 return 0;
719}
720
721void padctrl_config_pingroup(struct padctrl_config *config)
722{
723 enum pdrive_pingrp pad = config->padgrp;
724
725 padgrp_set_drvup_slwf(pad, config->slwf);
726 padgrp_set_drvdn_slwr(pad, config->slwr);
727 padgrp_set_drvup(pad, config->drvup);
728 padgrp_set_drvdn(pad, config->drvdn);
729 padgrp_set_lpmd(pad, config->lpmd);
730 padgrp_set_schmt(pad, config->schmt);
731 padgrp_set_hsm(pad, config->hsm);
732}
733
734void padgrp_config_table(struct padctrl_config *config, int len)
735{
736 int i;
737
738 for (i = 0; i < len; i++)
739 padctrl_config_pingroup(&config[i]);
740}