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git01.mediatek.com / filogic / uboot / 138914e6f1b7832d9ac632d1f25b712f551fa0f2 / . / board / logicpd / imx27lite / lowlevel_init.S
blob: 873634f1da56d69433c8d7fcdf34c51d3d463b69 [file] [log] [blame]
Ilya Yanok016b7022009-08-11 02:32:09 +0400[diff] [blame]1/*
2 * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
3 * Applications Processor Reference Manual, Rev. 0.2".
4 *
5 * (C) Copyright 2008 Eric Jarrige <eric.jarrige@armadeus.org>
6 * (C) Copyright 2009 Ilya Yanok <yanok@emcraft.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24
25#include <config.h>
26#include <version.h>
27#include <asm/macro.h>
28#include <asm/arch/imx-regs.h>
Stefano Babic2a1f1ac2011-09-05 04:32:28 +0000[diff] [blame]29#include <generated/asm-offsets.h>
Ilya Yanok016b7022009-08-11 02:32:09 +0400[diff] [blame]30
31SOC_ESDCTL_BASE_W: .word IMX_ESD_BASE
32SOC_SI_ID_REG_W: .word IMX_SYSTEM_CTL_BASE
33SDRAM_ESDCFG_T1_W: .word SDRAM_ESDCFG_REGISTER_VAL(0)
34SDRAM_ESDCFG_T2_W: .word SDRAM_ESDCFG_REGISTER_VAL(3)
35SDRAM_PRECHARGE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_PRECHARGE | \
36 ESDCTL_ROW13 | ESDCTL_COL10)
37SDRAM_AUTOREF_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_AUTO_REF | \
38 ESDCTL_ROW13 | ESDCTL_COL10)
39SDRAM_LOADMODE_CMD_W: .word (ESDCTL_SDE | ESDCTL_SMODE_LOAD_MODE | \
40 ESDCTL_ROW13 | ESDCTL_COL10)
41SDRAM_NORMAL_CMD_W: .word SDRAM_ESDCTL_REGISTER_VAL
42
43.macro init_aipi
44 /*
45 * setup AIPI1 and AIPI2
46 */
47 write32 AIPI1_PSR0, AIPI1_PSR0_VAL
48 write32 AIPI1_PSR1, AIPI1_PSR1_VAL
49 write32 AIPI2_PSR0, AIPI2_PSR0_VAL
50 write32 AIPI2_PSR1, AIPI2_PSR1_VAL
51
52.endm /* init_aipi */
53
54.macro init_clock
55 ldr r0, =CSCR
56 /* disable MPLL/SPLL first */
57 ldr r1, [r0]
58 bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
59 str r1, [r0]
60
61 write32 MPCTL0, MPCTL0_VAL
62 write32 SPCTL0, SPCTL0_VAL
63
64 write32 CSCR, CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
65
66 /*
67 * add some delay here
68 */
69 wait_timer 0x1000
70
71 /* peripheral clock divider */
72 write32 PCDR0, PCDR0_VAL
73 write32 PCDR1, PCDR1_VAL
74
75 /* Configure PCCR0 and PCCR1 */
76 write32 PCCR0, PCCR0_VAL
77 write32 PCCR1, PCCR1_VAL
78
79.endm /* init_clock */
80
81.macro sdram_init
82 ldr r0, SOC_ESDCTL_BASE_W
83 mov r2, #PHYS_SDRAM_1
84
85 /* Do initial reset */
86 mov r1, #ESDMISC_MDDR_DL_RST
87 str r1, [r0, #ESDMISC_ROF]
88
89 /* Hold for more than 200ns */
90 wait_timer 0x10000
91
92 /* Activate LPDDR iface */
93 mov r1, #ESDMISC_MDDREN
94 str r1, [r0, #ESDMISC_ROF]
95
96 /* Check The chip version TO1 or TO2 */
97 ldr r1, SOC_SI_ID_REG_W
98 ldr r1, [r1]
99 ands r1, r1, #0xF0000000
100 /* add Latency on CAS only for TO2 */
101 ldreq r1, SDRAM_ESDCFG_T2_W
102 ldrne r1, SDRAM_ESDCFG_T1_W
103 str r1, [r0, #ESDCFG0_ROF]
104
105 /* Run initialization sequence */
106 ldr r1, SDRAM_PRECHARGE_CMD_W
107 str r1, [r0, #ESDCTL0_ROF]
108 ldr r1, [r2, #SDRAM_ALL_VAL]
109
110 ldr r1, SDRAM_AUTOREF_CMD_W
111 str r1, [r0, #ESDCTL0_ROF]
112 ldr r1, [r2, #SDRAM_ALL_VAL]
113 ldr r1, [r2, #SDRAM_ALL_VAL]
114
115 ldr r1, SDRAM_LOADMODE_CMD_W
116 str r1, [r0, #ESDCTL0_ROF]
117 ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
118 add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
119 ldrb r1, [r3]
120
121 ldr r1, SDRAM_NORMAL_CMD_W
122 str r1, [r0, #ESDCTL0_ROF]
123
124#if (CONFIG_NR_DRAM_BANKS > 1)
125 /* 2nd sdram */
126 mov r2, #PHYS_SDRAM_2
127
128 /* Check The chip version TO1 or TO2 */
129 ldr r1, SOC_SI_ID_REG_W
130 ldr r1, [r1]
131 ands r1, r1, #0xF0000000
132 /* add Latency on CAS only for TO2 */
133 ldreq r1, SDRAM_ESDCFG_T2_W
134 ldrne r1, SDRAM_ESDCFG_T1_W
135 str r1, [r0, #ESDCFG1_ROF]
136
137 /* Run initialization sequence */
138 ldr r1, SDRAM_PRECHARGE_CMD_W
139 str r1, [r0, #ESDCTL1_ROF]
140 ldr r1, [r2, #SDRAM_ALL_VAL]
141
142 ldr r1, SDRAM_AUTOREF_CMD_W
143 str r1, [r0, #ESDCTL1_ROF]
144 ldr r1, [r2, #SDRAM_ALL_VAL]
145 ldr r1, [r2, #SDRAM_ALL_VAL]
146
147 ldr r1, SDRAM_LOADMODE_CMD_W
148 str r1, [r0, #ESDCTL1_ROF]
149 ldrb r1, [r2, #SDRAM_MODE_REGISTER_VAL]
150 add r3, r2, #SDRAM_EXT_MODE_REGISTER_VAL
151 ldrb r1, [r3]
152
153 ldr r1, SDRAM_NORMAL_CMD_W
154 str r1, [r0, #ESDCTL1_ROF]
155#endif /* CONFIG_NR_DRAM_BANKS > 1 */
156
157.endm /* sdram_init */
158
159.globl lowlevel_init
160lowlevel_init:
161
162 mov r10, lr
163
164 init_aipi
165
166 init_clock
167
168 sdram_init
169
170 mov pc,r10