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git01.mediatek.com / filogic / uboot / 136f3f44105183b9218c9f931c439a4d7da8c8a5 / . / arch / arm / include / asm / arch-tegra20 / clock-tables.h
blob: 6ec5ccb9363925beec3b5beaf0a45ff3f046ab41 [file] [log] [blame]
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]1/*
2 * Copyright (c) 2011 The Chromium OS Authors.
3 * Copyright (c) 2010-2012 NVIDIA Corporation <www.nvidia.com>
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23/* Tegra20 clock PLL tables */
24
25#ifndef _CLOCK_TABLES_H_
26#define _CLOCK_TABLES_H_
27
28/* The PLLs supported by the hardware */
29enum clock_id {
30 CLOCK_ID_FIRST,
31 CLOCK_ID_CGENERAL = CLOCK_ID_FIRST,
32 CLOCK_ID_MEMORY,
33 CLOCK_ID_PERIPH,
34 CLOCK_ID_AUDIO,
35 CLOCK_ID_USB,
36 CLOCK_ID_DISPLAY,
37
38 /* now the simple ones */
39 CLOCK_ID_FIRST_SIMPLE,
40 CLOCK_ID_XCPU = CLOCK_ID_FIRST_SIMPLE,
41 CLOCK_ID_EPCI,
42 CLOCK_ID_SFROM32KHZ,
43
44 /* These are the base clocks (inputs to the Tegra SOC) */
45 CLOCK_ID_32KHZ,
46 CLOCK_ID_OSC,
47
48 CLOCK_ID_COUNT, /* number of clocks */
49 CLOCK_ID_NONE = -1,
50};
51
52/* The clocks supported by the hardware */
53enum periph_id {
54 PERIPH_ID_FIRST,
55
56 /* Low word: 31:0 */
57 PERIPH_ID_CPU = PERIPH_ID_FIRST,
58 PERIPH_ID_RESERVED1,
59 PERIPH_ID_RESERVED2,
60 PERIPH_ID_AC97,
61 PERIPH_ID_RTC,
62 PERIPH_ID_TMR,
63 PERIPH_ID_UART1,
64 PERIPH_ID_UART2,
65
66 /* 8 */
67 PERIPH_ID_GPIO,
68 PERIPH_ID_SDMMC2,
69 PERIPH_ID_SPDIF,
70 PERIPH_ID_I2S1,
71 PERIPH_ID_I2C1,
72 PERIPH_ID_NDFLASH,
73 PERIPH_ID_SDMMC1,
74 PERIPH_ID_SDMMC4,
75
76 /* 16 */
77 PERIPH_ID_TWC,
78 PERIPH_ID_PWM,
79 PERIPH_ID_I2S2,
80 PERIPH_ID_EPP,
81 PERIPH_ID_VI,
82 PERIPH_ID_2D,
83 PERIPH_ID_USBD,
84 PERIPH_ID_ISP,
85
86 /* 24 */
87 PERIPH_ID_3D,
88 PERIPH_ID_IDE,
89 PERIPH_ID_DISP2,
90 PERIPH_ID_DISP1,
91 PERIPH_ID_HOST1X,
92 PERIPH_ID_VCP,
93 PERIPH_ID_RESERVED30,
94 PERIPH_ID_CACHE2,
95
96 /* Middle word: 63:32 */
97 PERIPH_ID_MEM,
98 PERIPH_ID_AHBDMA,
99 PERIPH_ID_APBDMA,
100 PERIPH_ID_RESERVED35,
101 PERIPH_ID_KBC,
102 PERIPH_ID_STAT_MON,
103 PERIPH_ID_PMC,
104 PERIPH_ID_FUSE,
105
106 /* 40 */
107 PERIPH_ID_KFUSE,
108 PERIPH_ID_SBC1,
109 PERIPH_ID_SNOR,
110 PERIPH_ID_SPI1,
111 PERIPH_ID_SBC2,
112 PERIPH_ID_XIO,
113 PERIPH_ID_SBC3,
114 PERIPH_ID_DVC_I2C,
115
116 /* 48 */
117 PERIPH_ID_DSI,
118 PERIPH_ID_TVO,
119 PERIPH_ID_MIPI,
120 PERIPH_ID_HDMI,
121 PERIPH_ID_CSI,
122 PERIPH_ID_TVDAC,
123 PERIPH_ID_I2C2,
124 PERIPH_ID_UART3,
125
126 /* 56 */
127 PERIPH_ID_RESERVED56,
128 PERIPH_ID_EMC,
129 PERIPH_ID_USB2,
130 PERIPH_ID_USB3,
131 PERIPH_ID_MPE,
132 PERIPH_ID_VDE,
133 PERIPH_ID_BSEA,
134 PERIPH_ID_BSEV,
135
136 /* Upper word 95:64 */
137 PERIPH_ID_SPEEDO,
138 PERIPH_ID_UART4,
139 PERIPH_ID_UART5,
140 PERIPH_ID_I2C3,
141 PERIPH_ID_SBC4,
142 PERIPH_ID_SDMMC3,
143 PERIPH_ID_PCIE,
144 PERIPH_ID_OWR,
145
146 /* 72 */
147 PERIPH_ID_AFI,
148 PERIPH_ID_CORESIGHT,
149 PERIPH_ID_RESERVED74,
150 PERIPH_ID_AVPUCQ,
151 PERIPH_ID_RESERVED76,
152 PERIPH_ID_RESERVED77,
153 PERIPH_ID_RESERVED78,
154 PERIPH_ID_RESERVED79,
155
156 /* 80 */
157 PERIPH_ID_RESERVED80,
158 PERIPH_ID_RESERVED81,
159 PERIPH_ID_RESERVED82,
160 PERIPH_ID_RESERVED83,
161 PERIPH_ID_IRAMA,
162 PERIPH_ID_IRAMB,
163 PERIPH_ID_IRAMC,
164 PERIPH_ID_IRAMD,
165
166 /* 88 */
167 PERIPH_ID_CRAM2,
Lucas Stache6941782012-09-25 09:59:12 +0000[diff] [blame]168 PERIPH_ID_SYNC_CLK_DOUBLER,
169 PERIPH_ID_CLK_M_DOUBLER,
170 PERIPH_ID_RESERVED91,
171 PERIPH_ID_SUS_OUT,
172 PERIPH_ID_DEV2_OUT,
173 PERIPH_ID_DEV1_OUT,
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]174
175 PERIPH_ID_COUNT,
176 PERIPH_ID_NONE = -1,
177};
178
Lucas Stachf7ee2a42012-09-25 20:21:13 +0000[diff] [blame]179enum pll_out_id {
180 PLL_OUT1,
181 PLL_OUT2,
182 PLL_OUT3,
183 PLL_OUT4
184};
185
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]186/* Converts a clock number to a clock register: 0=L, 1=H, 2=U */
187#define PERIPH_REG(id) ((id) >> 5)
188
189/* Mask value for a clock (within PERIPH_REG(id)) */
190#define PERIPH_MASK(id) (1 << ((id) & 0x1f))
191
192/* return 1 if a PLL ID is in range, and not a simple PLL */
193#define clock_id_is_pll(id) ((id) >= CLOCK_ID_FIRST && \
194 (id) < CLOCK_ID_FIRST_SIMPLE)
195
Tom Warren795f9d72013-01-23 14:01:01 -0700[diff] [blame]196/* return 1 if a peripheral ID is in range */
197#define clock_periph_id_isvalid(id) ((id) >= PERIPH_ID_FIRST && \
198 (id) < PERIPH_ID_COUNT)
199
Tom Warrenab371962012-09-19 15:50:56 -0700[diff] [blame]200#endif /* _CLOCK_TABLES_H_ */