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Dan Murphybb5a5662016-05-02 15:45:58 -05001* Texas Instruments - dp83867 Giga bit ethernet phy
2
3Required properties:
4 - reg - The ID number for the phy, usually a small integer
5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h
6 for applicable values
7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
8 for applicable values
9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h
10 for applicable values
Janine Hagemanned51bfc2018-08-28 08:25:37 +020011 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to
12 compensate for the board being designed with the lanes swapped.
13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the
14 TX/RX lanes.
Grygorii Strashkoa5efed62019-11-18 23:04:42 +020015 - ti,clk-output-sel - Muxing option for CLK_OUT pin. See dt-bindings/net/ti-dp83867.h
16 for applicable values. The CLK_OUT pin can also
17 be disabled by this property. When omitted, the
18 PHY's default will be left as is.
Dan Murphybb5a5662016-05-02 15:45:58 -050019
20Default child nodes are standard Ethernet PHY device
21nodes as described in doc/devicetree/bindings/net/ethernet.txt
22
23Example:
24
25 ethernet-phy@0 {
26 reg = <0>;
27 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>;
28 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_75_NS>;
29 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
Janine Hagemanned51bfc2018-08-28 08:25:37 +020030 enet-phy-lane-no-swap;
Janine Hagemann1c2ba092018-08-28 08:25:39 +020031 ti,clk-output-sel = <DP83867_CLK_O_SEL_CHN_A_TCLK>;
Dan Murphybb5a5662016-05-02 15:45:58 -050032 };
33
34Datasheet can be found:
35http://www.ti.com/product/DP83867IR/datasheet