Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 2 | /* |
| 3 | * Based on corenet_ds.c |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <command.h> |
Simon Glass | 0af6e2d | 2019-08-01 09:46:52 -0600 | [diff] [blame] | 8 | #include <env.h> |
Simon Glass | a7b5130 | 2019-11-14 12:57:46 -0700 | [diff] [blame] | 9 | #include <init.h> |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 10 | #include <netdev.h> |
| 11 | #include <linux/compiler.h> |
| 12 | #include <asm/mmu.h> |
| 13 | #include <asm/processor.h> |
| 14 | #include <asm/cache.h> |
| 15 | #include <asm/immap_85xx.h> |
| 16 | #include <asm/fsl_law.h> |
| 17 | #include <asm/fsl_serdes.h> |
| 18 | #include <asm/fsl_portals.h> |
| 19 | #include <asm/fsl_liodn.h> |
| 20 | #include <fm_eth.h> |
| 21 | #include <pci.h> |
| 22 | |
| 23 | #include "cyrus.h" |
| 24 | #include "../common/eeprom.h" |
| 25 | |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 26 | #define GPIO_OPENDRAIN 0x30000000 |
| 27 | #define GPIO_DIR 0x3c000004 |
| 28 | #define GPIO_INITIAL 0x30000000 |
| 29 | #define GPIO_VGA_SWITCH 0x00001000 |
| 30 | |
| 31 | int checkboard(void) |
| 32 | { |
| 33 | printf("Board: CYRUS\n"); |
| 34 | |
| 35 | return 0; |
| 36 | } |
| 37 | |
| 38 | int board_early_init_f(void) |
| 39 | { |
| 40 | ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
| 41 | ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); |
| 42 | |
| 43 | /* |
| 44 | * Only use DDR1_MCK0/3 and DDR2_MCK0/3 |
| 45 | * disable DDR1_MCK1/2/4/5 and DDR2_MCK1/2/4/5 to reduce |
| 46 | * the noise introduced by these unterminated and unused clock pairs. |
| 47 | */ |
| 48 | setbits_be32(&gur->ddrclkdr, 0x001B001B); |
| 49 | |
| 50 | /* Set GPIO reset lines to open-drain, tristate */ |
| 51 | setbits_be32(&pgpio->gpdat, GPIO_INITIAL); |
| 52 | setbits_be32(&pgpio->gpodr, GPIO_OPENDRAIN); |
| 53 | |
| 54 | /* Set GPIO Direction */ |
| 55 | setbits_be32(&pgpio->gpdir, GPIO_DIR); |
| 56 | |
| 57 | return 0; |
| 58 | } |
| 59 | |
| 60 | int board_early_init_r(void) |
| 61 | { |
| 62 | fsl_lbc_t *lbc = LBC_BASE_ADDR; |
| 63 | |
| 64 | out_be32(&lbc->lbcr, 0); |
| 65 | /* 1 clock LALE cycle */ |
| 66 | out_be32(&lbc->lcrr, 0x80000000 | CONFIG_SYS_LBC_LCRR); |
| 67 | |
| 68 | set_liodns(); |
| 69 | |
| 70 | #ifdef CONFIG_SYS_DPAA_QBMAN |
Ahmed Mansour | aa270b4 | 2017-12-15 16:01:00 -0500 | [diff] [blame] | 71 | setup_qbman_portals(); |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 72 | #endif |
| 73 | print_lbc_regs(); |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | int misc_init_r(void) |
| 78 | { |
| 79 | return 0; |
| 80 | } |
| 81 | |
| 82 | int ft_board_setup(void *blob, bd_t *bd) |
| 83 | { |
| 84 | phys_addr_t base; |
| 85 | phys_size_t size; |
| 86 | |
| 87 | ft_cpu_setup(blob, bd); |
| 88 | |
Simon Glass | da1a134 | 2017-08-03 12:22:15 -0600 | [diff] [blame] | 89 | base = env_get_bootm_low(); |
| 90 | size = env_get_bootm_size(); |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 91 | |
| 92 | fdt_fixup_memory(blob, (u64)base, (u64)size); |
| 93 | |
| 94 | #ifdef CONFIG_PCI |
| 95 | pci_of_setup(blob, bd); |
| 96 | #endif |
| 97 | |
| 98 | fdt_fixup_liodn(blob); |
Sriram Dash | 9fd465c | 2016-09-16 17:12:15 +0530 | [diff] [blame] | 99 | fsl_fdt_fixup_dr_usb(blob, bd); |
Andy Fleming | 3c98e7b | 2015-11-04 15:48:32 -0600 | [diff] [blame] | 100 | |
| 101 | #ifdef CONFIG_SYS_DPAA_FMAN |
| 102 | fdt_fixup_fman_ethernet(blob); |
| 103 | #endif |
| 104 | |
| 105 | return 0; |
| 106 | } |
| 107 | |
| 108 | int mac_read_from_eeprom(void) |
| 109 | { |
| 110 | init_eeprom(CONFIG_SYS_EEPROM_BUS_NUM, |
| 111 | CONFIG_SYS_I2C_EEPROM_ADDR, |
| 112 | CONFIG_SYS_I2C_EEPROM_ADDR_LEN); |
| 113 | |
| 114 | return mac_read_from_eeprom_common(); |
| 115 | } |