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git01.mediatek.com / filogic / uboot / 1333f5e328c61eba5ff039429ac538c113d9d90e / . / board / freescale / ls1046afrwy / eth.c
blob: 9f8bd928509d3e14673b4d3f1bbc9483597fbbe6 [file] [log] [blame]
Vabhav Sharma51641912019-06-06 12:35:28 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright 2019 NXP
4 */
5#include <common.h>
6#include <asm/io.h>
7#include <netdev.h>
8#include <fm_eth.h>
9#include <fsl_dtsec.h>
10#include <fsl_mdio.h>
11#include <malloc.h>
12
13#include "../common/fman.h"
14
15int board_eth_init(bd_t *bis)
16{
17#ifdef CONFIG_FMAN_ENET
18 struct memac_mdio_info dtsec_mdio_info;
19 struct mii_dev *dev;
20 u32 srds_s1;
21 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
22
23 srds_s1 = in_be32(&gur->rcwsr[4]) &
24 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
25 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
26
27 dtsec_mdio_info.regs =
28 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
29
30 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
31
32 /* Register the 1G MDIO bus */
33 fm_memac_mdio_init(bis, &dtsec_mdio_info);
34
35 /* QSGMII on lane B, MAC 6/5/10/1 */
36 fm_info_set_phy_address(FM1_DTSEC6, QSGMII_PORT1_PHY_ADDR);
37 fm_info_set_phy_address(FM1_DTSEC5, QSGMII_PORT2_PHY_ADDR);
38 fm_info_set_phy_address(FM1_DTSEC10, QSGMII_PORT3_PHY_ADDR);
39 fm_info_set_phy_address(FM1_DTSEC1, QSGMII_PORT4_PHY_ADDR);
40
41 switch (srds_s1) {
42 case 0x3040:
43 break;
44 default:
45 printf("Invalid SerDes protocol 0x%x for LS1046AFRWY\n",
46 srds_s1);
47 break;
48 }
49
50 dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
51 fm_info_set_mdio(FM1_DTSEC6, dev);
52 fm_info_set_mdio(FM1_DTSEC5, dev);
53 fm_info_set_mdio(FM1_DTSEC10, dev);
54 fm_info_set_mdio(FM1_DTSEC1, dev);
55
56 cpu_eth_init(bis);
57#endif
58
59 return pci_eth_init(bis);
60}
61
62#ifdef CONFIG_FMAN_ENET
63int fdt_update_ethernet_dt(void *blob)
64{
65 u32 srds_s1;
66 int i, prop;
67 int offset, nodeoff;
68 const char *path;
69 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
70
71 srds_s1 = in_be32(&gur->rcwsr[4]) &
72 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
73 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
74
75 /* Cycle through all aliases */
76 for (prop = 0; ; prop++) {
77 const char *name;
78
79 /* FDT might have been edited, recompute the offset */
80 offset = fdt_first_property_offset(blob,
81 fdt_path_offset(blob,
82 "/aliases")
83 );
84 /* Select property number 'prop' */
85 for (i = 0; i < prop; i++)
86 offset = fdt_next_property_offset(blob, offset);
87
88 if (offset < 0)
89 break;
90
91 path = fdt_getprop_by_offset(blob, offset, &name, NULL);
92 nodeoff = fdt_path_offset(blob, path);
93
94 switch (srds_s1) {
95 case 0x3040:
96 if (!strcmp(name, "ethernet1"))
97 fdt_status_disabled(blob, nodeoff);
98 if (!strcmp(name, "ethernet2"))
99 fdt_status_disabled(blob, nodeoff);
100 if (!strcmp(name, "ethernet3"))
101 fdt_status_disabled(blob, nodeoff);
102 if (!strcmp(name, "ethernet6"))
103 fdt_status_disabled(blob, nodeoff);
104 break;
105 default:
106 printf("%s:Invalid SerDes prtcl 0x%x for LS1046AFRWY\n",
107 __func__, srds_s1);
108 break;
109 }
110 }
111
112 return 0;
113}
114#endif